Year |
Citation |
Score |
2023 |
Chiang KJ, Dong S, Cheng CK, Jung TP. Using EEG signals to assess workload during memory retrieval in a real-world scenario. Journal of Neural Engineering. PMID 37040738 DOI: 10.1088/1741-2552/accbed |
0.462 |
|
2016 |
Wang YT, Nakanishi M, Wang Y, Wei CS, Cheng CK, Jung TP. An Online Brain-Computer Interface Based on SSVEPs Measured from Non-Hair-Bearing Areas. Ieee Transactions On Neural Systems and Rehabilitation Engineering : a Publication of the Ieee Engineering in Medicine and Biology Society. PMID 27254871 DOI: 10.1109/Tnsre.2016.2573819 |
0.718 |
|
2016 |
Zhuang H, Yu W, Weng SH, Kang I, Lin JH, Zhang X, Coutts R, Cheng CK. Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1681-1694. DOI: 10.1109/Tcad.2016.2523908 |
0.577 |
|
2016 |
Mei Q, Schoenmaker W, Weng SH, Zhuang H, Cheng CK, Chen Q. An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 832-843. DOI: 10.1109/Tcad.2015.2488494 |
0.563 |
|
2016 |
Zhuang H, Wang X, Chen Q, Chen P, Cheng CK. From Circuit Theory, Simulation to SPICEDiego: A Matrix Exponential Approach for Time-Domain Analysis of Large-Scale Circuits Ieee Circuits and Systems Magazine. 16: 16-34. DOI: 10.1109/Mcas.2016.2549947 |
0.351 |
|
2016 |
Chen Q, Schoenmaker W, Weng SH, Cheng CK, Chen GH, Jiang LJ, Wong N. A fast time-domain EM-TCAD coupled simulation framework via matrix exponential with stiffness reduction International Journal of Circuit Theory and Applications. 44: 833-850. DOI: 10.1002/Cta.2109 |
0.559 |
|
2015 |
Zhang X, Wang YT, Wang Y, Jung TP, Huang M, Cheng CK, Mandell AJ. Ultra-slow frequency bands reflecting potential coherence between neocortical brain regions. Neuroscience. 289: 71-84. PMID 25592429 DOI: 10.1016/J.Neuroscience.2014.12.050 |
0.692 |
|
2015 |
Lu J, Chen P, Chang CC, Sha L, Huang DJH, Teng CC, Cheng CK. Place: Electrostatics-based placement using fast fourier transform and nesterov's method Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2699873 |
0.558 |
|
2015 |
Lu J, Zhuang H, Chen P, Chang H, Chang CC, Wong YC, Sha L, Huang D, Luo Y, Teng CC, Cheng CK. EPlace-MS: Electrostatics-based placement for mixed-size circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 685-698. DOI: 10.1109/Tcad.2015.2391263 |
0.543 |
|
2014 |
Wang YT, Huang KC, Wei CS, Huang TY, Ko LW, Lin CT, Cheng CK, Jung TP. Developing an EEG-based on-line closed-loop lapse detection and mitigation system. Frontiers in Neuroscience. 8: 321. PMID 25352773 DOI: 10.3389/Fnins.2014.00321 |
0.71 |
|
2014 |
Weng SH, Zhang Y, Buckwalter JF, Cheng CK. Energy efficiency optimization through codesign of the transmitter and receiver in high-speed On-chip interconnects Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 938-942. DOI: 10.1109/Tvlsi.2013.2255070 |
0.575 |
|
2014 |
Hu X, Du P, Weng SH, Cheng CK. Worst case noise prediction with nonzero current transition times for power grid planning Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 607-620. DOI: 10.1109/Tvlsi.2013.2252210 |
0.665 |
|
2014 |
Zhang X, Liu Y, Hu X, Cheng CK. Ratio of the worst case noise and the impedance of power distribution network Ieee Transactions On Components, Packaging and Manufacturing Technology. 4: 1325-1334. DOI: 10.1109/Tcpmt.2014.2329003 |
0.325 |
|
2013 |
Wang YT, Wang Y, Cheng CK, Jung TP. Developing stimulus presentation on mobile devices for a truly portable SSVEP-based BCI. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2013: 5271-4. PMID 24110925 DOI: 10.1109/EMBC.2013.6610738 |
0.709 |
|
2013 |
Huang L, Huang X, Wang YT, Wang Y, Jung TP, Cheng CK. Empirical mode decomposition improves detection of SSVEP. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2013: 3901-4. PMID 24110584 DOI: 10.1109/EMBC.2013.6610397 |
0.691 |
|
2013 |
Hu X, Du P, Buckwalter JF, Cheng CK. Modeling and analysis of power distribution networks in 3-D ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 354-366. DOI: 10.1109/Tvlsi.2012.2183904 |
0.552 |
|
2013 |
Wang Y, Wong N, Wang YT, Huang X, Huang L, Jung TP, Mandell AJ, Cheng CK. Study of visual stimulus waveforms via forced van der Pol oscillator model for SSVEP-based brain-computer interfaces 2013 International Conference On Communications, Circuits and Systems, Icccas 2013. 2: 475-479. DOI: 10.1109/ICCCAS.2013.6765386 |
0.678 |
|
2012 |
Wang YT, Wang Y, Cheng CK, Jung TP. Measuring steady-state visual evoked potentials from non-hair-bearing areas. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2012: 1806-9. PMID 23366262 DOI: 10.1109/EMBC.2012.6346301 |
0.699 |
|
2012 |
Weng S, Chen Q, Cheng C. Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1180-1193. DOI: 10.1109/Tcad.2012.2189396 |
0.542 |
|
2012 |
Wang Y, Hu X, Cheng C, Pang GKH, Wong N. Corrigendum to “A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints” [Jan 12 109-120] Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 452-452. DOI: 10.1109/Tcad.2012.2186340 |
0.444 |
|
2012 |
Chen Q, Weng S, Cheng C. A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1031-1040. DOI: 10.1109/Tcad.2012.2184761 |
0.557 |
|
2012 |
Wang Y, Hu X, Cheng C, Pang GKH, Wong N. A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 109-120. DOI: 10.1109/Tcad.2011.2167328 |
0.489 |
|
2012 |
Wang YT, Cheng CK, Huang KC, Lin CT, Wang Y, Jung TP. Cell-phone based Drowsiness Monitoring and Management system 2012 Ieee Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems For Better Life and Better Environment, Biocas 2012 - Conference Publications. 200-203. DOI: 10.1109/BioCAS.2012.6418462 |
0.704 |
|
2011 |
Zhang Y, Hu X, Deutsch A, Engin AE, Buckwalter JF, Cheng CK. Prediction and comparison of high-performance on-chip global interconnection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1154-1166. DOI: 10.1109/Tvlsi.2010.2047415 |
0.505 |
|
2011 |
Zhang L, Zhang Y, Chen H, Yao B, Hamilton K, Cheng C. On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals Ieee Transactions On Very Large Scale Integration Systems. 19: 520-524. DOI: 10.1109/Tvlsi.2009.2035322 |
0.506 |
|
2011 |
Zhang L, Yu W, Zhang Y, Wang R, Deutsch A, Katopis GA, Dreps DM, Buckwalter J, Kuh ES, Cheng CK. Analysis and optimization of low-power passive equalizers for cpu-memory links Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 1406-1420. DOI: 10.1109/Tcpmt.2011.2157149 |
0.695 |
|
2011 |
Wang R, Zhang Y, Chou N, Young EFY, Cheng C, Graham R. Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 167-179. DOI: 10.1109/Tcad.2010.2097170 |
0.566 |
|
2010 |
Zeng S, Yu W, Hong X, Cheng C. Efficient Power Network Analysis with Modeling of Inductive Effects Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 93: 1196-1203. DOI: 10.1587/Transfun.E93.A.1196 |
0.349 |
|
2010 |
Wang R, Cheng CK, Young E. Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1835420.1835426 |
0.514 |
|
2010 |
Zhang W, Zhang L, Shayan A, Yu W, Hu X, Zhu Z, Engin E, Cheng CK. On-chip power network optimization with decoupling capacitors and controlled-ESRs Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 119-124. DOI: 10.1109/ASPDAC.2010.5419910 |
0.364 |
|
2009 |
Zeng S, Yu W, Shi J, Hong X, Cheng C. Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 92: 1476-1484. DOI: 10.1587/Transfun.E92.A.1476 |
0.315 |
|
2009 |
Yu W, Shi R, Cheng CK. Accurate eye diagram prediction based on step response and its application to low-power equalizer design Ieice Transactions On Electronics. 444-452. DOI: 10.1587/Transele.E92.C.444 |
0.345 |
|
2009 |
Zhang Y, Hu X, Deutsch A, Engin AE, Buckwalter JF, Cheng CK. Prediction of high-performance on-chip global interconnection International Workshop On System Level Interconnect Prediction, Slip. 61-68. DOI: 10.1145/1572471.1572482 |
0.44 |
|
2009 |
Zhu Y, Hu Y, Taylor MB, Cheng C. Energy and switch area optimizations for FPGA global routing architectures Acm Transactions On Design Automation of Electronic Systems. 14: 13. DOI: 10.1145/1455229.1455242 |
0.566 |
|
2009 |
Zhang W, Yu W, Hu X, Zhang L, Shi R, Peng H, Zhu Z, Chua-Eoan L, Murgai R, Shibuya T, Ito N, Cheng C. Efficient Power Network Analysis Considering Multidomain Clock Gating Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1348-1358. DOI: 10.1109/Tcad.2009.2024711 |
0.635 |
|
2009 |
Zhang Y, Zhang L, Deutsch A, Katopis GA, Dreps DM, Buckwalter JF, Kuh ES, Cheng CK. Design methodology of high performance on-chip global interconnect using terminated transmission-line Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 451-458. DOI: 10.1109/ISQED.2009.4810337 |
0.582 |
|
2009 |
Zhang L, Zhang Y, Tsuchiya A, Hashimoto M, Kuh ES, Cheng CK. High performance on-chip differential signaling using passive compensation for global communication Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 385-390. DOI: 10.1109/ASPDAC.2009.4796511 |
0.548 |
|
2008 |
Zhu Y, Shayan A, Zhang W, Chen TL, Jung TP, Duann JR, Makeig S, Cheng CK. Analyzing high-density ECG signals using ICA. Ieee Transactions On Bio-Medical Engineering. 55: 2528-37. PMID 18990622 DOI: 10.1109/Tbme.2008.2001262 |
0.636 |
|
2008 |
Shi R, Yu W, Zhu Y, Cheng CK, Kuh ES. Efficient and accurate eye diagram prediction for high speed signaling Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 655-661. DOI: 10.1109/ICCAD.2008.4681646 |
0.57 |
|
2008 |
Zhang Y, Zhang L, Deutsch A, Katopis GA, Dreps DM, Buckwalter JF, Kuh ES, Cheng CK. On-chip bus signaling using passive compensation Electrical Performance of Electronic Packaging, Epep. 33-36. DOI: 10.1109/EPEP.2008.4675869 |
0.6 |
|
2008 |
Hashimoto M, Siriporn J, Tsuchiya A, Zhu H, Cheng C. Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 91: 3474-3480. DOI: 10.1093/Ietfec/E91-A.12.3474 |
0.553 |
|
2007 |
Arani AS, Zhu Y, Zhang W, Jung TP, Duann JR, Makeig S, Cheng CK. Spatial density reduction in the study of the ECG signal using independent component analysis. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2007: 5497-500. PMID 18003256 DOI: 10.1109/IEMBS.2007.4353590 |
0.618 |
|
2007 |
Zhou S, Yao B, Chen H, Zhu Y, Hutton M, Collins T, Srinivasan S, Chou NC, Suaris P, Cheng CK. Efficient timing analysis with known false paths using biclique covering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 959-969. DOI: 10.1109/Tcad.2006.885737 |
0.616 |
|
2007 |
Zhu Z, Peng H, Cheng CK, Rouz K, Borah M, Kuh ES. Two-stage newton-raphson method for transistor-level simulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 881-895. DOI: 10.1109/Tcad.2006.884576 |
0.707 |
|
2006 |
Zhu H, Cheng C, Graham R. On the construction of zero-deficiency parallel prefix circuits with minimum depth Acm Transactions On Design Automation of Electronic Systems. 11: 387-409. DOI: 10.1145/1142155.1142162 |
0.53 |
|
2006 |
Li Z, Hong X, Zhou Q, Cai Y, Bian J, Yang HH, Pitchumani V, Cheng C. Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization Ieee Transactions On Circuits and Systems I-Regular Papers. 53: 2637-2646. DOI: 10.1109/Tcsi.2006.883857 |
0.306 |
|
2006 |
Zhu Y, Chen TL, Zhang W, Jung TP, Duann JR, Makeig S, Cheng CK. Noninvasive study of the human heart using independent component analysis Proceedings - Sixth Ieee Symposium On Bioinformatics and Bioengineering, Bibe 2006. 340-347. DOI: 10.1109/BIBE.2006.253299 |
0.404 |
|
2004 |
Wu X, Hong X, Cai Y, Luo Z, Cheng C, Gu J, Dai W. Area minimization of power distribution network using efficient nonlinear programming techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1086-1094. DOI: 10.1109/Tcad.2004.829809 |
0.351 |
|
2004 |
Jing T, Hong X, Xu J, Bao H, Cheng C, Gu J. UTACO: A Unified Timing and Congestion Optimization Algorithm for Standard Cell Global Routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 358-365. DOI: 10.1109/Tcad.2004.823354 |
0.318 |
|
2004 |
Chang CW, Hsiao MF, Hu B, Wang K, Marek-Sadowska M, Cheng CK, Chen SJ. Fast Postplacement Optimization Using Functional Symmetries Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 102-118. DOI: 10.1109/Tcad.2003.819904 |
0.362 |
|
2003 |
Yao B, Chen H, Cheng C, Graham R. Floorplan representations: Complexity and connections Acm Transactions On Design Automation of Electronic Systems. 8: 55-80. DOI: 10.1145/606603.606607 |
0.469 |
|
2002 |
Yang X, Cheng C, Ku WH, Carragher R. Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial Analog Integrated Circuits and Signal Processing. 31: 193-208. DOI: 10.1023/A:1015340523443 |
0.505 |
|
2001 |
Ma Y, Hong X, Dong S, Cai Y, Cheng C, Gu J. Floorplanning with abutment constraints based on corner block list Integration. 31: 65-77. DOI: 10.1016/S0167-9260(01)00022-0 |
0.367 |
|
2000 |
Chen S, Cheng C. Tutorial on VLSI Partitioning Vlsi Design. 11: 175-218. DOI: 10.1155/2000/53913 |
0.317 |
|
1999 |
Xu J, Guo P, Cheng C. Sequence-pair approach for rectilinear module placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 484-493. DOI: 10.1109/43.752931 |
0.325 |
|
1999 |
Lillis J, Cheng C. Timing optimization for multisource nets: characterization and optimal repeater insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 322-331. DOI: 10.1109/43.748162 |
0.319 |
|
1998 |
Li J, Cheng CK. Routability improvement using dynamic interconnect architecture Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 498-501. DOI: 10.1109/92.711321 |
0.314 |
|
1997 |
Hong X, Xue T, Huang J, Cheng CK, Kuh ES. TIGER: An efficient timing-driven global router for gate array and standard cell layout design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1323-1331. DOI: 10.1109/43.663822 |
0.64 |
|
1996 |
Carragher RJ, Cheng CK, Xiong XM, Fujita M, Paturi R. Solving the net matching problem in high-performance chip design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 902-911. DOI: 10.1109/43.511570 |
0.327 |
|
1996 |
Lillis J, Cheng C, Lin T-Y. Optimal wire sizing and buffer insertion for low power and a generalized delay model Ieee Journal of Solid-State Circuits. 31: 437-447. DOI: 10.1109/4.494206 |
0.361 |
|
1995 |
Chou NC, Cheng CK. On General Zero-Skew Clock Net Construction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 141-146. DOI: 10.1109/92.365461 |
0.322 |
|
1995 |
Fan J, Zaleta D, Lee SH, Cheng CK. Physical Models and Algorithms for Optoelectronic MCM Layout Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 124-135. DOI: 10.1109/92.365459 |
0.303 |
|
1995 |
Chou N, Liu L, Cheng C, Dai W, Lindelof R. Local ratio cut and set covering partitioning for huge logic emulation systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1085-1092. DOI: 10.1109/43.406710 |
0.329 |
|
1994 |
Zaleta D, Fan J, Kress BC, Lee SH, Cheng C. Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for multichip module interconnects Applied Optics. 33: 1444-1456. PMID 20862170 DOI: 10.1364/Ao.33.001444 |
0.32 |
|
1994 |
Chou N, Cheng C, Russell TC. Dynamic probe scheduling optimization for MCM substrate test Ieee Transactions On Components, Packaging, and Manufacturing Technology: Part B. 17: 182-189. DOI: 10.1109/96.330431 |
0.301 |
|
1994 |
Yeh C, Liu L, Cheng C, Hu TC, Ahmed S, Liddel M. Block-oriented programmable design with switching network interconnect Ieee Transactions On Very Large Scale Integration Systems. 2: 45-53. DOI: 10.1109/92.273149 |
0.334 |
|
1994 |
Yeh CW, Cheng CK, Lin TTY. A General Purpose, Multiple-Way Partitioning Algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 1480-1488. DOI: 10.1109/43.331405 |
0.313 |
|
1994 |
Yao S, Chou N, Cheng C, Hu TC. A multi-probe approach for MCM substrate testing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 110-121. DOI: 10.1109/43.273744 |
0.308 |
|
1992 |
Cheng C. The optimal partitioning of networks Networks. 22: 297-315. DOI: 10.1002/Net.3230220307 |
0.302 |
|
1984 |
Cheng CK, Kuh ES. Module Placement Based on Resistive Network Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 3: 218-225. DOI: 10.1109/Tcad.1984.1270078 |
0.623 |
|
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