Year |
Citation |
Score |
2019 |
Sarin SK, Choudhury A, Sharma MK, Maiwall R, Al Mahtab M, Rahman S, Saigal S, Saraf N, Soin AS, Devarbhavi H, Kim DJ, Dhiman RK, Duseja A, Taneja S, Eapen CE, ... Goel A, et al. Acute-on-chronic liver failure: consensus recommendations of the Asian Pacific association for the study of the liver (APASL): an update. Hepatology International. PMID 31172417 DOI: 10.1007/s12072-019-09946-3 |
0.318 |
|
2016 |
Dalela D, Gupta P, Dalela D, Bansal A, Govil T, Goel A, Sankhwar SN. Meatal Occlusive Disease in Adult Males: Are There Any Clinical Variations. Urologia Internationalis. PMID 27160440 DOI: 10.1159/000446221 |
0.364 |
|
2011 |
Kulkarni JP, Goel A, Ndai P, Roy K. A read-disturb-free, differential sensing 1R/1W Port, 8T bitcell array Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1727-1730. DOI: 10.1109/Tvlsi.2010.2055169 |
0.715 |
|
2011 |
Goel A, Gupta SK, Roy K. Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs Ieee Transactions On Electron Devices. 58: 296-308. DOI: 10.1109/Ted.2010.2090421 |
0.684 |
|
2011 |
Goel A, Ghosh S, Meterelliyoz M, Parkhurst J, Roy K. Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost Proceedings of the Asian Test Symposium. 486-491. DOI: 10.1109/ATS.2011.100 |
0.728 |
|
2010 |
Li J, Ndai P, Goel A, Salahuddin S, Roy K. Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1710-1723. DOI: 10.1109/Tvlsi.2009.2027907 |
0.767 |
|
2010 |
Ndai P, Goel A, Roy K. A scalable circuit-architecture co-design to improve memory yield for high-performance processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1209-1219. DOI: 10.1109/Tvlsi.2009.2022628 |
0.772 |
|
2010 |
Meterelliyoz M, Goel A, Kulkarni JP, Roy K. Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 186-187. DOI: 10.1109/ISSCC.2010.5433991 |
0.735 |
|
2010 |
Moradi F, Augustine C, Goel A, Karakonstantis G, Cao TV, Wisland D, Mahmoodi H, Roy K. Data-dependant sense-amplifier flip-flop for low power applications Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617468 |
0.735 |
|
2009 |
Goel A, Ndai P, Kulkarni JP, Roy K. REad/access-preferred (REAP) SRAM - Architecture-aware bit cell design for improved yield and lower V MIN Proceedings of the Custom Integrated Circuits Conference. 503-506. DOI: 10.1109/CICC.2009.5280794 |
0.736 |
|
2009 |
Li J, Ndai P, Goel A, Liu H, Roy K. An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 841-846. DOI: 10.1109/ASPDAC.2009.4796585 |
0.769 |
|
2007 |
Datta A, Goel A, Cakici RT, Mahmoodi H, Lekshmanan D, Roy K. Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1957-1966. DOI: 10.1109/Tcad.2007.896320 |
0.689 |
|
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