| Year |
Citation |
Score |
| 2020 |
Park J, Oh TW, Jung S. pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation Ieee Transactions On Very Large Scale Integration Systems. 28: 1079-1083. DOI: 10.1109/Tvlsi.2019.2963704 |
0.372 |
|
| 2020 |
Lim S, Song B, Jung S. Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability Ieee Transactions On Information Forensics and Security. 15: 2798-2807. DOI: 10.1109/Tifs.2020.2976623 |
0.376 |
|
| 2019 |
Yoon NA, Jung SJ, Choi SH, Ryu JH, Mani M, Lee UH, Vo MT, Jeon DY, Chung SW, Lee BJ, Koh YW, Park SE, Shin YJ, Kang SS, Cho WJ, et al. DRG2 supports the growth of primary tumors and metastases of melanoma by enhancing VEGF-A expression. The Febs Journal. PMID 31693298 DOI: 10.1111/febs.15125 |
0.403 |
|
| 2019 |
Na T, Song B, Choi S, Kim JP, Kang SH, Jung S. Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS Ieee Transactions On Very Large Scale Integration Systems. 27: 2548-2555. DOI: 10.1109/Tvlsi.2019.2925931 |
0.385 |
|
| 2019 |
Kim SM, Song B, Jung S. Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM Ieee Transactions On Very Large Scale Integration Systems. 27: 2413-2422. DOI: 10.1109/Tvlsi.2019.2920630 |
0.395 |
|
| 2019 |
Ko J, Yang Y, Kim J, Lee C, Min Y, Chun J, Kim M, Jung S. Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory Ieee Transactions On Very Large Scale Integration Systems. 27: 1828-1839. DOI: 10.1109/Tvlsi.2019.2912081 |
0.361 |
|
| 2019 |
Park HK, Choi TH, Ahn HK, Jung S. Thermoelectric Cooling Read for Resolving Read Disturb With Inrush Current Issue in OTS-PRAM Ieee Transactions On Nanotechnology. 18: 421-431. DOI: 10.1109/Tnano.2019.2910846 |
0.381 |
|
| 2019 |
Choi TH, Oh TW, Jung S. Parasitic $RC$ Aware Delay Corner Model for Sub-10-nm Logic Circuit Design Ieee Transactions On Electron Devices. 66: 191-199. DOI: 10.1109/Ted.2018.2882773 |
0.314 |
|
| 2019 |
Song B, Choi S, Kang SH, Jung S. Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 2963-2972. DOI: 10.1109/Tcsi.2019.2913009 |
0.401 |
|
| 2019 |
Jeong H, Park J, Song SC, Jung S. Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time Ieee Journal of Solid-State Circuits. 54: 2304-2315. DOI: 10.1109/Jssc.2019.2907774 |
0.348 |
|
| 2019 |
Jeong H, Oh SH, Oh TW, Kim H, Park CN, Rim W, Song T, Jung S. Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving Ieee Journal of Solid-State Circuits. 54: 896-906. DOI: 10.1109/Jssc.2018.2883725 |
0.392 |
|
| 2018 |
Jung D, Ryu K, Park J, Jung S. All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate Ieee Transactions On Very Large Scale Integration Systems. 26: 1015-1025. DOI: 10.1109/Tvlsi.2018.2801030 |
0.338 |
|
| 2018 |
Jeong H, Oh TW, Song SC, Jung S. Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation Ieee Transactions On Very Large Scale Integration Systems. 26: 609-620. DOI: 10.1109/Tvlsi.2017.2777788 |
0.357 |
|
| 2018 |
Na T, Song B, Kim JP, Kang SH, Jung S. Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 163-174. DOI: 10.1109/Tcsi.2017.2712363 |
0.341 |
|
| 2018 |
Jung D, Kim K, Joo S, Jung S. 0.293-mm 2 Fast Transient Response Hysteretic Quasi- $V^{2}$ DC–DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35- $\mu$ m CMOS Ieee Journal of Solid-State Circuits. 53: 1844-1855. DOI: 10.1109/Jssc.2018.2805884 |
0.349 |
|
| 2017 |
Oh TW, Jeong H, Kang K, Park J, Yang Y, Jung S. Power-Gated 9T SRAM Cell for Low-Energy Operation Ieee Transactions On Very Large Scale Integration Systems. 25: 1183-1187. DOI: 10.1109/Tvlsi.2016.2623601 |
0.387 |
|
| 2017 |
Song B, Na T, Kim JP, Kang SH, Jung S. A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area Ieee Transactions On Circuits and Systems Ii-Express Briefs. 64: 700-704. DOI: 10.1109/Tcsii.2016.2594827 |
0.35 |
|
| 2017 |
Oh TW, Jeong H, Park J, Jung S. Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 2737-2747. DOI: 10.1109/Tcsi.2017.2702587 |
0.376 |
|
| 2017 |
Choi TH, Jeong H, Yang Y, Park J, Jung S. SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis Ieee Transactions On Circuits and Systems I: Regular Papers. 64: 2063-2072. DOI: 10.1109/Tcsi.2017.2685634 |
0.336 |
|
| 2017 |
Ko J, Yang Y, Kim J, Oh Y, Park HK, Jung S. Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 1444-1455. DOI: 10.1109/Tcsi.2017.2654270 |
0.361 |
|
| 2017 |
Na T, Song B, Kim JP, Kang SH, Jung S. Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS Ieee Journal of Solid-State Circuits. 52: 496-504. DOI: 10.1109/Jssc.2016.2612235 |
0.379 |
|
| 2017 |
Park JH, Jung DH, Jung S. GRO‐TDC with gate‐switch‐based delay cell halving resolution limit International Journal of Circuit Theory and Applications. 45: 2211-2225. DOI: 10.1002/Cta.2344 |
0.393 |
|
| 2016 |
Ju MJ, Jeon IY, Kim HM, Choi JI, Jung SM, Seo JM, Choi IT, Kang SH, Kim HS, Noh MJ, Lee JJ, Jeong HY, Kim HK, Kim YH, Baek JB. Edge-selenated graphene nanoplatelets as durable metal-free catalysts for iodine reduction reaction in dye-sensitized solar cells. Science Advances. 2: e1501459. PMID 27386557 DOI: 10.1126/Sciadv.1501459 |
0.605 |
|
| 2016 |
Byun SH, Lee JH, Jung NC, Choi HJ, Song JY, Seo HG, Choi J, Jung SY, Kang S, Choi YS, Chung JH, Lim DS. Rosiglitazone-mediated dendritic cells ameliorate collagen-induced arthritis in mice. Biochemical Pharmacology. PMID 27208887 DOI: 10.1016/j.bcp.2016.05.009 |
0.607 |
|
| 2016 |
An Y, Jung D, Ryu K, Yim HS, Jung S. All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator Ieee Transactions On Very Large Scale Integration Systems. 24: 3232-3242. DOI: 10.1109/Tvlsi.2016.2550603 |
0.321 |
|
| 2016 |
Na T, Kim JP, Kang SH, Jung SO. Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2536639 |
0.362 |
|
| 2016 |
Choi S, Na T, Kim J, Kim JP, Kang SH, Jung SO. Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2532878 |
0.412 |
|
| 2016 |
Jeong H, Park J, Oh TW, Rim W, Song T, Kim G, Won H, Jung S. Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM Ieee Transactions On Circuits and Systems Ii-Express Briefs. 63: 1059-1063. DOI: 10.1109/Tcsii.2016.2548100 |
0.394 |
|
| 2016 |
Kim K, Jeong H, Park J, Jung SO. Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution Ieee Transactions On Circuits and Systems Ii: Express Briefs. 63: 964-968. DOI: 10.1109/Tcsii.2016.2536258 |
0.383 |
|
| 2016 |
Na T, Kim JP, Kang SH, Jung S. Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM Ieee Transactions On Circuits and Systems Ii-Express Briefs. 63: 578-582. DOI: 10.1109/Tcsii.2016.2530883 |
0.403 |
|
| 2016 |
Yang Y, Jeong H, Song SC, Wang J, Yeap G, Jung S. Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology Ieee Transactions On Circuits and Systems. 63: 1023-1032. DOI: 10.1109/Tcsi.2016.2556118 |
0.374 |
|
| 2015 |
Ryu K, Jung J, Jung DH, Kim JH, Jung SO. High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2453366 |
0.312 |
|
| 2015 |
Na T, Kim J, Song B, Kim JP, Kang SH, Jung SO. An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2453192 |
0.383 |
|
| 2015 |
Jung DH, Ryu K, Park JH, Jung SO. All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2423312 |
0.374 |
|
| 2015 |
Yang Y, Park J, Song SC, Wang J, Yeap G, Jung SO. Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation with Enhanced Read Performance in 22-nm FinFET Technology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2748-2752. DOI: 10.1109/Tvlsi.2014.2367234 |
0.417 |
|
| 2015 |
An YJ, Jung DH, Ryu K, Woo SH, Jung SO. An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1508-1517. DOI: 10.1109/Tvlsi.2014.2344112 |
0.314 |
|
| 2015 |
Jeong H, Kim T, Song T, Kim G, Jung S. Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM Ieee Transactions On Very Large Scale Integration Systems. 23: 1370-1374. DOI: 10.1109/Tvlsi.2014.2337958 |
0.34 |
|
| 2015 |
Kang H, Kim J, Jeong H, Yang YH, Jung S. Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory Ieee Transactions On Very Large Scale Integration Systems. 23: 752-765. DOI: 10.1109/Tvlsi.2014.2321897 |
0.35 |
|
| 2015 |
Park JH, Kang H, Jung DH, Ryu K, Jung SO. Level-converting retention flip-flop for reducing standby power in ZigBee SoCs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 413-421. DOI: 10.1109/Tvlsi.2014.2311851 |
0.377 |
|
| 2015 |
Jeong H, Yang Y, Song SC, Wang J, Yeap G, Jung SO. Variation-aware figure of merit for integrated circuit in near-threshold region Ieee Transactions On Electron Devices. 62: 1754-1759. DOI: 10.1109/Ted.2015.2424220 |
0.353 |
|
| 2015 |
Park J, Yang Y, Jeong H, Song SC, Wang J, Yeap G, Jung SO. Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation Ieee Transactions On Electron Devices. 62: 1698-1704. DOI: 10.1109/Ted.2015.2420681 |
0.389 |
|
| 2015 |
Na T, Kim J, Kim JP, Kang SH, Jung SO. A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 1109-1113. DOI: 10.1109/Tcsii.2015.2468993 |
0.34 |
|
| 2015 |
Jung DH, An YJ, Ryu K, Park JH, Jung SO. All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 1023-1027. DOI: 10.1109/Tcsii.2015.2456111 |
0.368 |
|
| 2015 |
Ko J, Kim J, Choi Y, Park HK, Jung S. Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM Ieee Transactions On Circuits and Systems. 62: 2091-2102. DOI: 10.1109/Tcsi.2015.2452352 |
0.355 |
|
| 2015 |
Song B, Na T, Kim J, Kim JP, Kang SH, Jung SO. Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 1776-1784. DOI: 10.1109/Tcsi.2015.2427931 |
0.397 |
|
| 2015 |
Yang Y, Park J, Song SC, Wang J, Yeap G, Jung SO. SRAM Design for 22-nm ETSOI technology: Selective cell current boosting and asymmetric back-gate write-assist circuit Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 1538-1545. DOI: 10.1109/Tcsi.2015.2416814 |
0.41 |
|
| 2015 |
Jeong H, Kim T, Kang K, Song T, Kim G, Won HS, Jung SO. Switching pMOS sense amplifier for high-density low-voltage single-ended SRAM Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 1555-1563. DOI: 10.1109/Tcsi.2015.2415171 |
0.391 |
|
| 2015 |
Jeong H, Kim T, Yang Y, Song T, Kim G, Won HS, Jung SO. Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 1062-1070. DOI: 10.1109/Tcsi.2015.2388837 |
0.351 |
|
| 2014 |
Na T, Kim J, Kim JP, Kang S, Jung S. An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM Ieee Transactions On Very Large Scale Integration Systems. 22: 1620-1624. DOI: 10.1109/Tvlsi.2013.2294095 |
0.374 |
|
| 2014 |
Kim J, Ryu K, Kim JP, Kang S, Jung S. STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies Ieee Transactions On Very Large Scale Integration Systems. 22: 1630-1634. DOI: 10.1109/Tvlsi.2013.2272587 |
0.389 |
|
| 2014 |
Na T, Woo S, Kim J, Jeong H, Jung S. Comparative Study of Various Latch-Type Sense Amplifiers Ieee Transactions On Very Large Scale Integration Systems. 22: 425-429. DOI: 10.1109/Tvlsi.2013.2239320 |
0.377 |
|
| 2014 |
Kim J, Na T, Kim JP, Kang SH, Jung S. A Split-Path Sensing Circuit for Spin Torque Transfer MRAM Ieee Transactions On Circuits and Systems Ii-Express Briefs. 61: 193-197. DOI: 10.1109/Tcsii.2013.2296136 |
0.395 |
|
| 2014 |
Ryu K, Jung DH, Jung SO. Process-variation-calibrated multiphase delay locked loop with a loop-embedded duty cycle corrector Ieee Transactions On Circuits and Systems Ii: Express Briefs. 61: 1-5. DOI: 10.1109/Tcsii.2013.2291052 |
0.334 |
|
| 2014 |
Na T, Kim J, Kim JP, Kang S, Jung S. Reference-scheme study and novel reference scheme for deep submicrometer STT-RAM Ieee Transactions On Circuits and Systems. 61: 3376-3385. DOI: 10.1109/Tcsi.2014.2327337 |
0.337 |
|
| 2014 |
An YJ, Ryu K, Jung DH, Woo SH, Jung SO. An energy efficient time-domain temperature sensor for low-power on-chip thermal management Ieee Sensors Journal. 14: 104-110. DOI: 10.1109/Jsen.2013.2280647 |
0.31 |
|
| 2014 |
Jung Y, Kim J, Ryu K, Kim JP, Kang SH, Jung S. An MTJ-based non-volatile flip-flop for high-performance SoC International Journal of Circuit Theory and Applications. 42: 394-406. DOI: 10.1002/Cta.1859 |
0.315 |
|
| 2013 |
Park JH, Jung DH, Ryu K, Jung SO. ADDLL for clock-deskew buffer in high-performance SoCs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1368-1373. DOI: 10.1109/Tvlsi.2012.2210742 |
0.373 |
|
| 2013 |
Kang M, Kim J, Yang YH, Jung S. Dynamic mixed serial–parallel content addressable memory (DMSP CAM) International Journal of Circuit Theory and Applications. 41: 721-731. DOI: 10.1002/Cta.814 |
0.383 |
|
| 2012 |
Ryu K, Kim J, Jung J, Kim JP, Kang SH, Jung S. A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop Ieee Transactions On Very Large Scale Integration Systems. 20: 2044-2053. DOI: 10.1109/Tvlsi.2011.2172644 |
0.358 |
|
| 2012 |
Kim J, Ryu K, Kang SH, Jung S. A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM) Ieee Transactions On Very Large Scale Integration Systems. 20: 181-186. DOI: 10.1109/Tvlsi.2010.2088143 |
0.404 |
|
| 2012 |
Yang Y, Jeong H, Yang F, Wang J, Yeap G, Jung S. Read-Preferred SRAM Cell With Write-Assist Circuit Using Back-Gate ETSOI Transistors in 22-nm Technology Ieee Transactions On Electron Devices. 59: 2575-2581. DOI: 10.1109/Ted.2012.2205693 |
0.392 |
|
| 2012 |
Ryu K, Jung D, Jung S. A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator Ieee Transactions On Circuits and Systems. 59: 1860-1870. DOI: 10.1109/Tcsi.2011.2180453 |
0.305 |
|
| 2011 |
Park C, Song Y, Kang JH, Jung S, Yun I. Effects of Electrical Characteristics on the Non-Rectangular Gate Structure Variations for the Multifinger MOSFETs Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 352-358. DOI: 10.1109/Tcpmt.2010.2099532 |
0.314 |
|
| 2011 |
Song J, Kim J, Kang SH, Yoon S, Jung S. Sensing margin trend with technology scaling in MRAM International Journal of Circuit Theory and Applications. 39: 313-325. DOI: 10.1002/Cta.635 |
0.381 |
|
| 2010 |
Kim J, Song JH, Kang SH, Yoon SS, Jung S. Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits Ieice Transactions On Electronics. 93: 912-921. DOI: 10.1587/Transele.E93.C.912 |
0.381 |
|
| 2010 |
Jung DH, Ryu KH, Jung S. A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface Ieee Transactions On Consumer Electronics. 56: 2400-2405. DOI: 10.1109/Tce.2010.5681119 |
0.322 |
|
| 2010 |
Ryu KH, Jung DH, Jung S. A DLL based clock generator for low-power mobile SoCs Ieee Transactions On Consumer Electronics. 56: 1950-1956. DOI: 10.1109/Tce.2010.5606351 |
0.303 |
|
| 2010 |
Woo SH, Kang H, Park K, Jung SO. Offset voltage estimation model for latch-type sense amplifiers Iet Circuits, Devices and Systems. 4: 503-513. DOI: 10.1049/Iet-Cds.2010.0092 |
0.348 |
|
| 2009 |
Kang M, Jung S. Serial-Parallel Content Addressable Memory with a Conditional Driver (SPCwCD) Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 92: 318-321. DOI: 10.1587/Transfun.E92.A.318 |
0.328 |
|
| 2009 |
Hwang ME, Jung SO, Roy K. Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation Ieee Transactions On Circuits and Systems I: Regular Papers. 56: 1428-1441. DOI: 10.1109/Tcsi.2008.2006217 |
0.388 |
|
| 2008 |
Nho H, Yoon SS, Wong SS, Jung SO. Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 907-911. DOI: 10.1109/Tcsii.2008.923411 |
0.324 |
|
| 2008 |
Jung S, Yoon S. Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 91: 895-898. DOI: 10.1093/Ietfec/E91-A.3.895 |
0.338 |
|
| 2005 |
Yang G, Jung S, Baek K, Kim SH, Kim S, Kang S. A 32-bit carry lookahead adder using dual-path all-N logic Ieee Transactions On Very Large Scale Integration Systems. 13: 992-996. DOI: 10.1109/Tvlsi.2005.853605 |
0.349 |
|
| 2003 |
Kim K, Jung S, Kim T, Kang S. Minimum delay optimization for domino logic circuits---a coupling-aware approach Acm Transactions On Design Automation of Electronic Systems (Todaes). 8: 203-213. DOI: 10.1145/762488.762491 |
0.305 |
|
| 2003 |
Kim K, Jung S, Kim T, Saxena P, Liu CL, Kang S-S. Coupling delay optimization by temporal decorrelation using dual threshold voltage technique Ieee Transactions On Very Large Scale Integration Systems. 11: 879-887. DOI: 10.1109/Tvlsi.2003.817111 |
0.357 |
|
| 2003 |
Kim K, Jung S, Narayanan U, Liu CL, Kang S. Noise-aware interconnect power optimization in domino logic synthesis Ieee Transactions On Very Large Scale Integration Systems. 11: 79-89. DOI: 10.1109/Tvlsi.2002.801630 |
0.303 |
|
| 2003 |
Jung S, Kim K, Kang S. Timing constraints for domino logic gates with timing-dependent keepers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 96-103. DOI: 10.1109/Tcad.2002.805724 |
0.373 |
|
| 2002 |
Jung S, Kim K, Kang S. Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic Ieee Transactions On Very Large Scale Integration Systems. 10: 532-541. DOI: 10.1109/Tvlsi.2002.801625 |
0.356 |
|
| 2002 |
Kim C, Jung S, Baek K, Kang S. High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 49: 434-439. DOI: 10.1109/Tcsii.2002.802960 |
0.359 |
|
| 2002 |
Jung S, Kang S. High performance dynamic logic incorporating gate voltage controlled keeper structure for wide fan-in gates Electronics Letters. 38: 852-853. DOI: 10.1049/El:20020623 |
0.367 |
|
| 2001 |
Kim K, Jung S, Kim T, Kang S. Coupling-aware minimum delay optimisation for domino logic circuits Electronics Letters. 37: 813-814. DOI: 10.1049/El:20010554 |
0.312 |
|
| 2000 |
Jung S, Kang SM. Modular charge recycling pass transistor logic (MCRPL) Electronics Letters. 36: 404-405. DOI: 10.1049/El:20000386 |
0.352 |
|
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