Pranav P. Kalavade, Ph.D.
Affiliations: | 2003 | Stanford University, Palo Alto, CA |
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"Pranav Kalavade"Mean distance: 18.66
Parents
Sign in to add mentorKrishna C. Saraswat | grad student | 2003 | Stanford | |
(Novel device structures for CMOS scaling.) |
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Publications
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Cho H, Kapur P, Kalavade P, et al. (2008) A low-power, highly scalable, vertical double-gate MOSFET using novel processes Ieee Transactions On Electron Devices. 55: 632-639 |
Cho H, Kapur P, Kalavade P, et al. (2007) Highly scalable vertical double gate NOR flash memory Technical Digest - International Electron Devices Meeting, Iedm. 917-920 |
Cho H, Kapur P, Kalavade P, et al. (2006) A novel spacer process for sub-10-nm-thick vertical MOS and its integration with planar MOS device Ieee Transactions On Nanotechnology. 5: 554-563 |
Hergenrother JM, Wilk GD, Nigam T, et al. (2001) 50 nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO2 and Al2O3 gate dielectrics Technical Digest - International Electron Devices Meeting. 51-54 |
Toita M, Kalavade P, Saraswat KC. (2000) Control of Amorphous Silicon Crystallization Using Germanium Deposited by Low Pressure Chemical Vapor Deposition Mrs Proceedings. 609 |
Saraswat KC, Banerjee K, Joshi AR, et al. (2000) 3-D ICs: Motivation, performance analysis, and technology European Solid-State Circuits Conference. 406-414 |
Kalavade P, Saraswat KC. (2000) Novel sub-10nm transistor Annual Device Research Conference Digest. 71-72 |