Howard C. Luong
Affiliations: | Physics, General | Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong |
Area:
Electronics and Electrical EngineeringGoogle:
"Howard Luong"Mean distance: (not calculated yet)
Parents
Sign in to add mentorTheodore van Duzer | grad student | 1994 | UC Berkeley (E-Tree) | |
(Superconducting Flash-Type Analog-to-Digital Converters with Multi-Gigahertz Performance) |
Children
Sign in to add traineeChunbing Guo | grad student | 2001 | HKUST |
Shuzuo Lou | grad student | 2007 | HKUST |
Wenting Wang | grad student | 2007 | HKUST |
Sujiang Rong | grad student | 2010 | HKUST |
Wing L. Ng | grad student | 2012 | HKUST |
BETA: Related publications
See more...
Publications
You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect. |
Liu X, Luong HC. (2020) A 170-GHz 23.7% Tuning-Range CMOS Injection-Locked LO Generator With Third-Harmonic Enhancement Ieee Transactions On Microwave Theory and Techniques. 68: 2668-2678 |
Liu X, Luong HC. (2020) A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer With Frequency-Tracking Loop in 65-nm CMOS Ieee Journal of Solid-State Circuits. 55: 1051-1063 |
Lin C, Mirzaie N, Alzahmi A, et al. (2019) A Reconfigurable CMOS Power Amplifier Using Adaptive Biasing Technique for Wireless Monitoring Applications Journal of Semiconductor Technology and Science. 19: 511-516 |
Chae Y, Wicht B, Verbruggen B, et al. (2019) Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC) Ieee Journal of Solid-State Circuits. 54: 3243-3246 |
Liu X, Zhang H, Mok PKT, et al. (2019) A Multi-Loop-Controlled AC-Coupling Supply Modulator With a Mode-Switching CMOS PA in an EER System With Envelope Shaping Ieee Journal of Solid-State Circuits. 54: 1553-1563 |
Huang Z, Luong HC. (2019) An 82–107.6-GHz Integer- $N$ ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta–Sigma TDC Ieee Journal of Solid-State Circuits. 54: 358-367 |
Huang Z, Jiang B, Luong HC. (2018) A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 2118-2126 |
Wu L, Ng AWL, Zheng S, et al. (2017) A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration Ieee Transactions On Very Large Scale Integration Systems. 25: 2371-2382 |
Huang Z, Luong HC. (2017) Design and Analysis of Millimeter-Wave Digitally Controlled Oscillators With C-2C Exponentially Scaling Switched-Capacitor Ladder Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 1299-1307 |
Wu L, Leung HF, Luong HC. (2017) Design and Analysis of CMOS LNAs with Transformer Feedback for Wideband Input Matching and Noise Cancellation Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 1626-1635 |