Yu-Min Lee, Ph.D.
Affiliations: | 2003 | University of Wisconsin, Madison, Madison, WI |
Area:
Electronics and Electrical EngineeringGoogle:
"Yu-Min Lee"Mean distance: (not calculated yet)
Parents
Sign in to add mentor| Charlie C. Chen | grad student | 2003 | UW Madison | |
| (Efficient chip -level power grid networks simulation and optimization techniques.) | ||||
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Publications
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| Lee Y, Ho C. (2017) InTraSim: Incremental Transient Simulation of Power Grids Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 2052-2065 |
| Chiou H, Lee Y. (2016) Thermal Simulation for Two-Phase Liquid Cooling 3D-ICs Journal of Computational Chemistry. 4: 33-45 |
| Lee YM, Pan CW, Huang PY, et al. (2015) LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1250-1263 |
| Huang PY, Lee YM. (2009) Full-Chip thermal analysis for the early design stage via generalized integral transforms Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 613-626 |
| Lee Y, Cao Y, Chen T, et al. (2005) HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 797-806 |
| Lee Y, Chen CC-. (2003) The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1545-1550 |
| Lee YM, Chen CCP. (2002) Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1343-1352 |
| Lee Y, Chen CCP, Chang YW, et al. (2002) Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation Vlsi Design. 15: 587-594 |