Payman Zarkesh-Ha, Ph.D. - Publications

Affiliations: 
2001 Georgia Institute of Technology, Atlanta, GA 
Area:
Microelectronics/Microsystems

66 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Anwar F, Nogan J, Zarkesh-Ha P, Osinski M. Multilevel resistance in Ti/Pt/AlOx/HfOy/Ti/Pt/Ag resistive switching devices 2015 Ieee Nanotechnology Materials and Devices Conference, Nmdc 2015. DOI: 10.1109/NMDC.2015.7439273  1
2015 Neumann A, Ghasemi J, Nezhadbadeh S, Nie X, Zarkesh-Ha P, Brueck SR. CMOS-compatible plenoptic detector for LED lighting applications. Optics Express. 23: 23208-16. PMID 26368423 DOI: 10.1364/Oe.23.023208  1
2015 Ghasemi J, Neumann A, Nezhadbadeh S, Nie X, Zarkesh-Ha P, Brueck SRJ. A CMOS-compatible plenoptic sensor for smart lighting applications Conference On Lasers and Electro-Optics Europe - Technical Digest. 2015. DOI: 10.1364/CLEO_SI.2015.STh1I.6  1
2015 Hossain MM, Zarkesh-Ha P, Hayat MM. Linear mode CMOS compatible p-n junction avalanche photodiode with operating voltage below 9V 2015 Ieee Photonics Conference, Ipc 2015. 436-437. DOI: 10.1109/IPCon.2015.7323686  1
2015 Ghasemi J, Chowdhury AJ, Neumann A, Fahs B, Hella M, Brueck SRJ, Zarkesh-Ha P. A novel blue-enhanced photodetector using honeycomb structure 2015 Ieee Sensors - Proceedings. DOI: 10.1109/ICSENS.2015.7370557  1
2015 Zarkesh-Ha P, Edwards J, Szauter P. Avalanche ISFET: A highly sensitive pH sensor for genome sequencing Ieee Biomedical Circuits and Systems Conference: Engineering For Healthy Minds and Able Bodies, Biocas 2015 - Proceedings. DOI: 10.1109/BioCAS.2015.7348335  1
2015 Ghasemi J, Neumann A, Nezhadbadeh S, Nie X, Zarkesh-Ha P, Brueck SRJ. A CMOS-compatible plenoptic sensor for smart lighting applications Conference On Lasers and Electro-Optics Europe - Technical Digest. 2015.  1
2014 Atghiaee A, Masoumi N, Zarkesh-Ha P, Mehri M. Predictive application of PIDF and PPC for interconnects' crosstalk, TSV, and LER issues in UDSM ICs and nano-systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 438-443. DOI: 10.1109/Tvlsi.2013.2243849  1
2014 West J, Imani S, Lavrova O, Cavanaugh W, Ju J, Pupuhi K, Keshavmurthy S, Aarestad J, Zarkesh-Ha P. Reconfigurable power management using novel monolithically integrated CMOS-on-PV switch 2014 Ieee 40th Photovoltaic Specialist Conference, Pvsc 2014. 1389-1392. DOI: 10.1109/PVSC.2014.6925177  1
2014 Ghasemi J, Zarkesh-Ha P, Krishna S, Godoy SE, Hayat MM. A novel readout circuit for on-sensor multispectral classification Midwest Symposium On Circuits and Systems. 386-389. DOI: 10.1109/MWSCAS.2014.6908433  1
2014 Zarkesh-Ha P. An intelligent readout circuit for infrared multispectral remote sensing Midwest Symposium On Circuits and Systems. 153-156. DOI: 10.1109/MWSCAS.2014.6908375  1
2014 Hossain MM, Zarkesh-Ha P, David JPR, Hayat MM. Low breakdown voltage CMOS compatible p-n junction avalanche photodiode 2014 Ieee Photonics Conference, Ipc 2014. 170-171. DOI: 10.1109/IPCon.2014.6995302  1
2014 Ray S, Hella MM, Hossain MM, Zarkesh-Ha P, Hayat MM. Speed optimized large area avalanche photodetector in standard CMOS technology for visible light communication Proceedings of Ieee Sensors. 2014: 2147-2150. DOI: 10.1109/ICSENS.2014.6985463  1
2014 Butala PM, Elgala H, Little TDC, Zarkesh-Ha P. Multi-wavelength visible light communication system design 2014 Ieee Globecom Workshops, Gc Wkshps 2014. 530-535. DOI: 10.1109/GLOCOMW.2014.7063486  1
2013 Cugler Fiorante GR, Zarkesh-Ha P, Ghasemi J, Krishna S. Spatiooral tunable pixels for multi-spectral infrared imagers Midwest Symposium On Circuits and Systems. 317-320. DOI: 10.1109/MWSCAS.2013.6674649  1
2013 Ghasemi J, Zarkesh-Ha P, Fiorante GR, Krishna S. A new CMOS readout circuit approach for multispectral imaging 2013 Ieee Photonics Conference, Ipc 2013. 592-593. DOI: 10.1109/IPCon.2013.6656433  1
2013 Hossain MM, Ghasemi J, Zarkesh-Ha P, Hayat MM. Design, modeling and fabrication of a CMOS compatible p-n junction avalanche photodiode 2013 Ieee Photonics Conference, Ipc 2013. DOI: 10.1109/IPCon.2013.6656429  1
2013 Zarkesh-Ha P. Analysis of low-voltage mixed-signal circuits under device variations 2013 Ieee Faible Tension Faible Consommation, Ftfc 2013. DOI: 10.1109/FTFC.2013.6577756  1
2012 Jang WY, Hayat MM, Zarkesh-Ha P, Krishna S. Continuous time-varying biasing approach for spectrally tunable infrared detectors. Optics Express. 20: 29823-37. PMID 23388809 DOI: 10.1364/Oe.20.029823  1
2012 Shahi AAM, Zarkesh-Ha P, Elahi M. Comparison of variations in MOSFET versus CNFET in gigascale integrated systems Proceedings - International Symposium On Quality Electronic Design, Isqed. 378-383. DOI: 10.1109/ISQED.2012.6187521  1
2012 Shahi AAM, Zarkesh-Ha P. Prediction of gate delay variation for CNFET under CNT density variation Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 140-145. DOI: 10.1109/DFT.2012.6378214  1
2011 Jang WY, Hayat MM, Godoy SE, Bender SC, Zarkesh-Ha P, Krishna S. Data compressive paradigm for multispectral sensing using tunable DWELL mid-infrared detectors. Optics Express. 19: 19454-72. PMID 21996886 DOI: 10.1364/Oe.19.019454  1
2011 Zarkesh-Ha P, Shahi AAM. Stochastic analysis and design guidelines for CNFETs in gigascale integrated systems Ieee Transactions On Electron Devices. 58: 530-539. DOI: 10.1109/Ted.2010.2092780  1
2011 Bezerra GBP, Forrest S, Zarkesh-Ha P. Reducing energy and increasing performance with traffic optimization in many-core systems International Workshop On System Level Interconnect Prediction, Slip. DOI: 10.1109/SLIP.2011.6135429  1
2011 Jang WY, Hayat MM, Godoy SE, Zarkesh-Ha P, Bender SC, Krishna S. Compressive multispectral sensing algorithm with tunable quantum dots-in-a-well infrared photodetectors Ieee Photonic Society 24th Annual Meeting, Pho 2011. 147-148. DOI: 10.1109/Pho.2011.6110468  1
2011 Xu JF, Fiorante GRC, Zarkesh-Ha P, Krishna S. A Readout Integrated Circuit (ROIC) with hybrid source/sensor array Ieee Photonic Society 24th Annual Meeting, Pho 2011. 97-98. DOI: 10.1109/Pho.2011.6110443  1
2010 Zarkesh-Ha P, Jang W, Nguyen P, Khoshakhlagh A, Xu J. A reconfigurable ROIC for integrated infrared spectral sensing 2010 23rd Annual Meeting of the Ieee Photonics Society, Photinics 2010. 714-715. DOI: 10.1109/Photonics.2010.5699088  1
2010 Devarapalli SV, Zarkesh-Ha P, Suddarth SC. A robust and low power Dual Data Rate (DDR) flip-flop using C-elements Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 147-150. DOI: 10.1109/ISQED.2010.5450403  1
2010 Atghiaee A, Masoumi N, Zarkesh-Ha P. Nano-scale early-design-stage prediction for crosstalk-induced power Inec 2010 - 2010 3rd International Nanoelectronics Conference, Proceedings. 585-586. DOI: 10.1109/INEC.2010.5425183  1
2010 Helinski R, LeBoeuf T, Hoffman C, Zarkesh-Ha P. A linear digital VCO for Clock Data Recovery (CDR) applications 2010 Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2010 - Proceedings. 98-101. DOI: 10.1109/ICECS.2010.5724463  1
2010 Zarkesh-Ha P, Shahi AAM. Logic gate failure characterization for nanoelectronic EDA tools Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 16-23. DOI: 10.1109/DFT.2010.9  1
2010 Devarapalli SV, Zarkesh-Ha P, Suddarth SC. SEU-hardened dual data rate flip-flop using C-elements Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 167-171. DOI: 10.1109/DFT.2010.27  1
2010 Purushotham NN, Devarapalli SV, Lyke J, Zarkesh-Ha P. Self-healing adjustable memory system Aiaa Infotech At Aerospace 2010 1
2009 Ghaida RS, Doniger K, Zarkesh-Ha P. Random yield prediction based on a stochastic layout sensitivity model Ieee Transactions On Semiconductor Manufacturing. 22: 329-337. DOI: 10.1109/Tsm.2009.2024821  1
2009 Devarapalli SV, Zarkesh-Ha P, Suddarth SC. Scavenger: An adaptive design technique for low power ASIC/FPGA Icc2009 - International Conference of Computing in Engineering, Science and Information. 164-167. DOI: 10.1109/ICC.2009.14  1
2009 Ghaida RS, Zarkesh-Ha P. A layout sensitivity model for eestimating electromigration-vulnerable narrow interconnects Journal of Electronic Testing: Theory and Applications (Jetta). 25: 67-77. DOI: 10.1007/S10836-008-5079-X  1
2008 Jain V, Zarkesh-Ha P. Analytical noise-rejection model based on short channel MOSFET Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 401-406. DOI: 10.1109/ISQED.2008.4479765  1
2008 Mallajosyula A, Zarkesh-Ha P. A robust single event upset hardened clock distribution network Ieee International Integrated Reliability Workshop Final Report. 121-124. DOI: 10.1109/IRWS.2008.4796101  1
2007 Zarkesh-Ha P, Doniger K. Stochastic interconnect layout sensitivity model International Workshop On System Level Interconnect Prediction, Slip. 9-14. DOI: 10.1145/1231956.1231959  1
2007 Ghaida RS, Zarkesh-Ha P. Estimation of electromigration-aggravating narrow interconnects using a layout sensitivity model Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 59-67. DOI: 10.1109/DFT.2007.12  1
2007 Sarvari R, Naeemi A, Zarkesh-Ha P, Meindl JD. Design and optimization for nanoscale power distribution networks in gigascale systems Proceedings of the Ieee 2007 International Interconnect Technology Conference - Digest of Technical Papers. 190-192.  1
2007 Zarkesh-Ha P, Doniger K. Interconnect layout sensitivity and yield prediction Electronic Device Failure Analysis. 9: 6-13.  1
2004 Joyner JW, Zarkesh-Ha P, Meindl JD. Global interconnect design in a three-dimensional system-on-a-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 367-372. DOI: 10.1109/Tvlsi.2004.825835  1
2004 Zarkesh-Ha P, Doniger K, Loh W, Bendix P. Prediction of interconnect adjacency distribution: Derivation, validation, and applications International Workshop On System Level Interconnect Prediction, Slip. 99-106.  1
2003 Zarkesh-Ha P, Lakshminarayanan S, Doniger K, Loh W, Wright P. Impact of interconnect pattern density information on a 90 nm technology ASIC design flow Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 405-409. DOI: 10.1109/ISQED.2003.1194767  1
2003 Zarkesh-Ha P, Wright P, Lakshminarayanan S, Cheng CC, Loh W, Lynch W. Backend process optimization for 90 nm high-density ASIC chips Proceedings of the Ieee 2003 International Interconnect Technology Conference, Iitc 2003. 123-125. DOI: 10.1109/IITC.2003.1219731  1
2003 Zarkesh-Ha P, Doniger K, Loh W, Wright P. Prediction of Interconnect Pattern Density Distribution: Derivation, Validation, and Applications International Workshop On System Level Interconnect Prediction. 85-91.  1
2003 Zarkesh-Ha P, Doniger K, Loh W, Sun D, Stephani R, Priebe G. A compact model for analysis and design of on-chip power network with decoupling capacitors Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 84-89.  1
2002 Meindl JD, Davis JA, Zarkesh-Ha P, Patel CS, Martin KP, Kohl PA. Interconnect opportunities for gigascale integration Ibm Journal of Research and Development. 46: 245-263. DOI: 10.1147/Rd.462.0245  1
2001 Joyner JW, Venkatesan R, Zarkesh-Ha P, Davis JA, Meindl JD. Impact of three-dimensional architectures on interconnects in gigascale integration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 922-928. DOI: 10.1109/92.974905  1
2001 Meindl JD, Venkatesan R, Davis JA, Joyner J, Naeemi A, Zarkesh-Ha P, Bakir M, Mulé T, Kohl PA, Martin KP. Interconnecting device opportunities for gigascale integration (GSI) Technical Digest - International Electron Devices Meeting. 525-528.  1
2001 Joyner JW, Zarkesh-Ha P, Meindl JD. A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC) Proceedings of the Annual Ieee International Asic Conference and Exhibit. 147-151.  1
2001 Naeemi A, Patel CS, Bakir MS, Zarkesh-Ha P, Martin KP, Meindl JD. Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC) Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 280-281.  1
2001 Saint-Laurent M, Zarkesh-Ha P, Swaminathan M, Meindl JD. Optimal clock distribution with an array of phase-locked loops for multiprocessor chips Midwest Symposium On Circuits and Systems. 1: 454-457.  1
2000 Joyner JW, Zarkesh-Ha P, Davis JA, Meindl JD. A three-dimensional stochastic wire-length distribution for variable separation of strata Proceedings of the Ieee 2000 International Interconnect Technology Conference, Iitc 2000. 126-128. DOI: 10.1109/IITC.2000.854301  1
2000 Chen Q, Davis JA, Zarkesh-Ha P, Meindl JD. A novel via blockage model and its implications Proceedings of the Ieee 2000 International Interconnect Technology Conference, Iitc 2000. 15-17. DOI: 10.1109/IITC.2000.854267  1
2000 Chen Q, Davis JA, Zarkesh-Ha P, Meindl JD. A compact physical via blockage model Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 689-692. DOI: 10.1109/92.902263  1
2000 Zarkesh-Ha P, Davis JA, Meindl JD. Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 649-659. DOI: 10.1109/92.902259  1
2000 Zarkesh-Ha P, Davis JA, Loh W, Meindl JD. Prediction of interconnect fan-out distribution using Rent's rule International Workshop On System-Level Interconnect Prediction (Slip 2000). 107-112.  1
2000 Joyner JW, Zarkesh-Ha P, Davis JA, Meindl JD. Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures International Workshop On System-Level Interconnect Prediction (Slip 2000). 123-127.  1
2000 Naeemi A, Zarkesh-Ha P, Patel CS, Meindl JD. Performance improvement using on-board wires for on-chip interconnects Ieee Topical Meeting On Electrical Performance of Electronic Packaging. 325-328.  1
2000 Zarkesh-Ha P, Meindl JD. Integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) Digest of Technical Papers - Symposium On Vlsi Technology. 194-195.  1
1999 Zarkesh-Ha P, Meindl JD. Asymptotically zero power dissipation gigahertz clock distribution networks Ieee Topical Meeting On Electrical Performance of Electronic Packaging. 57-60.  1
1999 Zarkesh-Ha P, Mule T, Meindl JD. Characterization and modeling of clock skew with process variations Proceedings of the Custom Integrated Circuits Conference. 441-444.  1
1998 Zarkesh-Ha P, Davis JA, Lob W, Meindl JD. On a pin versus gate relationship for heterogeneous systems: Heterogeneous Rent's rule Proceedings of the Custom Integrated Circuits Conference. 93-96.  1
1998 Zarkesh-Ha P, Meindl JD. Stochastic net length distributions for global interconnects in a heterogeneous system-on-a-chip Digest of Technical Papers - Symposium On Vlsi Technology. 44-45.  1
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