Keith A. Bowman, Ph.D. - Publications

2001 Georgia Institute of Technology, Atlanta, GA 

15 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2007 Lopez G, Murali R, Sarvari R, Bowman K, Davis J, Meindl J. The impact of size effects and copper interconnect process variations on the maximum critical path delay of single and multi-core microprocessors Proceedings of the Ieee 2007 International Interconnect Technology Conference - Digest of Technical Papers. 40-42.  1
2006 Sekar DC, Venkatesan R, Bowman KA, Joshi A, Davis JA, Meindl JD. Optimal repeaters for sub-50nm interconnect networks 2006 International Interconnect Technology Conference, Iitc. 199-201. DOI: 10.1109/IITC.2006.1648687  1
2003 Chen Q, Bowman KA, Harrell EM, Meindl JD. Double jeopardy in the nanoscale court? Ieee Circuits and Devices Magazine. 19: 28-34. DOI: 10.1109/Mcd.2003.1175105  1
2001 Venkatesan R, Davis JA, Bowman KA, Meindl JD. Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI) Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 899-912. DOI: 10.1109/92.974903  1
2001 Bowman KA, Wang L, Tang X, Meindl JD. A circuit-level perspective of the optimum gate oxide thickness Ieee Transactions On Electron Devices. 48: 1800-1810. DOI: 10.1109/16.936710  1
2001 Bowman KA, Meindl JD. Impact of within-die parameter fluctuations on future maximum clock frequency distributions Proceedings of the Custom Integrated Circuits Conference. 229-232.  1
2000 Venkatesan R, Davis JA, Bowman KA, Meindl JD. Optimal repeater insertion for n-tier multilevel interconnect architectures Proceedings of the Ieee 2000 International Interconnect Technology Conference, Iitc 2000. 132-134. DOI: 10.1109/IITC.2000.854303  1
2000 Bowman KA, Wang L, Tang X, Meindl JD. Oxide thickness scaling limit for optimum CMOS logic circuit performance European Solid-State Device Research Conference. 300-303. DOI: 10.1109/ESSDERC.2000.194774  1
2000 Bhavnagarwala AJ, Austin BL, Bowman KA, Meindl JD. A minimum total power methodology for projecting limits on CMOS GSI Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 235-251. DOI: 10.1109/92.845891  1
2000 Bowman KA, Tang X, Eble JC, Meindl JD. Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance Ieee Journal of Solid-State Circuits. 35: 1186-1193. DOI: 10.1109/4.859508  1
2000 Venkatesan R, Davis JA, Bowman KA, Meindl JD. Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion Proceedings of the International Symposium On Low Power Electronics and Design. 167-172.  1
2000 Davis JA, Venkatesan R, Bowman K, Meindl JD. Gigascale integration (GSI) interconnect limits and N-tier multilevel interconnect architectural solutions International Workshop On System-Level Interconnect Prediction (Slip 2000). 147-148.  1
1999 Bowman KA, Austin BL, Eble JC, Tang X, Meindl JD. Physical alpha-power law MOSFET model Ieee Journal of Solid-State Circuits. 34: 1410-1414. DOI: 10.1109/4.792617  1
1999 Tang X, Bowman KA, Eble JC, De VK, Meind JD. Impact of random dopant placement on CMOS delay and power dissipation European Solid-State Device Research Conference. 13: 184-187.  1
1998 Austin BL, Bowman KA, Tang X, Meindl JD. Low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI) Proceedings of the Annual Ieee International Asic Conference and Exhibit. 125-129.  1
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