Blanca L. Austin, Ph.D. - Publications

Affiliations: 
2001 Georgia Institute of Technology, Atlanta, GA 
Area:
Microelectronics/Microsystems

14 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2004 Murali R, Austin BL, Wang L, Meindl JD. Short-channel modeling of bulk accumulation MOSFETs Ieee Transactions On Electron Devices. 51: 940-947. DOI: 10.1109/Ted.2004.828276  1
2002 Murali R, Austin BL, Wang L, Meindl JD. Scaled accumulation FETS for ultra-low power logic Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 371-375. DOI: 10.1109/ASIC.2002.1158087  1
2002 Murali R, Wang L, Austin BL, Meindl JD. Low-power circuit advantages of the scaled accumulation FET Proceedings - Ieee International Symposium On Circuits and Systems. 5: V/201-V/204.  1
2002 Murali R, Austin BL, Meindl JD. A tick based methodology for rapid predictive circuit modeling Proceedings - Ieee International Symposium On Circuits and Systems. 3: III/791-III/794.  1
2000 Bhavnagarwala AJ, Austin BL, Bowman KA, Meindl JD. A minimum total power methodology for projecting limits on CMOS GSI Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 235-251. DOI: 10.1109/92.845891  1
2000 Bhavnagarwala AJ, Austin B, Kapoor A, Meindl JD. CMOS system-on-a-chip voltage scaling beyond 50 nm Proceedings of the Ieee Great Lakes Symposium On Vlsi. 7-12.  1
1999 Bowman KA, Austin BL, Eble JC, Tang X, Meindl JD. Physical alpha-power law MOSFET model Ieee Journal of Solid-State Circuits. 34: 1410-1414. DOI: 10.1109/4.792617  1
1998 Austin BL, Tang X, Meindl JD, Dennen M, Richards WR. Threshold voltage roll-off model for low power bulk accumulation MOSFETs Proceedings of the Annual Ieee International Asic Conference and Exhibit. 175-179.  1
1998 Bhavnagarwala AJ, Austin B, Meindl JD. Minimum supply voltage for bulk Si CMOS GSI Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. [d]100-102.  1
1998 Austin BL, Bowman KA, Tang X, Meindl JD. Low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI) Proceedings of the Annual Ieee International Asic Conference and Exhibit. 125-129.  1
1997 Meindl JD, De VK, Wills DS, Eble JC, Tang X, Davis JA, Austin B, Bhavnagarwala AJ. Impact of stochastic dopant and interconnect distributions on gigascale integration Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 40: 232-233.  1
1997 Bhavnagarwala AJ, Austin B, Meindl JD. Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010 Proceedings of the Annual Ieee International Asic Conference and Exhibit. 185-188.  1
1996 Bhavnagarwala AJ, De VK, Austin B, Meindl JD. Circuit techniques for low power CMOS GSI Ieee Symposium On Low Power Electronics. 193-196.  1
1996 Bhavnagarwala AJ, De VK, Austin B, Meindl JD. Optimal circuit design for low power CMOS GSI Proceedings of the Annual Ieee International Asic Conference and Exhibit. 313-316.  1
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