Scott J. Weber, Ph.D. - Publications

Affiliations: 
2005 University of California, Berkeley, Berkeley, CA, United States 
Area:
Computer Architecture & Engineering (ARC); Design, Modeling and Analysis (DMA); Scientific Computing (SCI)

7 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2007 Mihal A, Weber S, Keutzer K. Sub-RISC processors Customizable Embedded Processors. 303-336. DOI: 10.1016/B978-012369526-0/50014-0  0.704
2005 Shah N, Plishker W, Ravindran K, Gries M, Weber S, Mihal A, Kulkarni C, Moskewicz M, Sauer C, Keutzer K. Successfully deploying the ASIP Building Asips: the Mescal Methodology. 179-225. DOI: 10.1007/0-387-26128-1_6  0.721
2005 Weber S, Jin Y, Gries M, Sauer C, Moskewicz M. Efficiently describing and evaluating the ASIPs Building Asips: the Mescal Methodology. 85-130. DOI: 10.1007/0-387-26128-1_4  0.392
2004 Weber SJ, Moskewicz MW, Gries M, Sauer C, Keutzer K. Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures Second Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and Systems Synthesis, Codes+Isss 2004. 18-23.  0.367
2004 Sauer C, Gries M, Gomez JI, Weber S, Keutzer K. Developing a flexible interface for RapidIO, hypertransport, and PCI-express International Conference On Parallel Computing in Electrical Engineering: Workshop On System Design Automation, Sda, Parelec 2004. 129-134.  0.439
2002 Mihal A, Kulkarni C, Moskewicz M, Tsai M, Shah N, Weber S, Jin Y, Kentzer K, Vissers K, Sauer C, Malik S. Developing architectural platforms: A disciplined approach Ieee Design and Test of Computers. 19: 6-16. DOI: 10.1109/Mdt.2002.1047739  0.309
2001 Tasiran S, Fallah F, Chinnery DG, Weber SJ, Keutzer K. A functional validation technique: Biased-random simulation guided by observability-based coverage Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 82-88.  0.648
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