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Shantanu Dutt - Publications

Affiliations: 
University of Illinois at Chicago, Chicago, IL, United States 
Area:
Computer Science
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24 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Ren H, Dutt S. Fast and near-optimal timing-driven cell sizing under cell area and leakage power constraints using a simplified discrete network flow algorithm Vlsi Design. 2013. DOI: 10.1155/2013/474601  0.518
2011 Dutt S, Ren H. Discretized network flow techniques for timing and wire-length driven incremental placement with white-space satisfaction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1277-1290. DOI: 10.1109/Tvlsi.2010.2050632  0.373
2011 Ren H, Dutt S. A provably high-probability white-space satisfaction algorithm with good performance for standard-cell detailed placement Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1291-1304. DOI: 10.1109/Tvlsi.2010.2047876  0.392
2011 Ren H, Dutt S. Effective power optimization under timing and voltage-island constraints via simultaneous VDD, Vth assignments, gate sizing, and placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 746-759. DOI: 10.1109/Tcad.2010.2097330  0.361
2009 Dutt S, Li L. Trust-based design and check of FPGA circuits using two-level randomized ECC structures Acm Transactions On Reconfigurable Technology and Systems. 2. DOI: 10.1145/1502781.1508209  0.311
2008 Dutt S, Verma V, Suthar V. Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 309-326. DOI: 10.1109/Tcad.2007.906992  0.325
2008 Ren H, Dutt S. Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closuret Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 93-100. DOI: 10.1109/ICCAD.2008.4681557  0.476
2007 Mahapatra NR, Dutt S. An efficient delay-optimal distributed termination detection algorithm Journal of Parallel and Distributed Computing. 67: 1047-1066. DOI: 10.1016/J.Jpdc.2007.05.013  0.354
2002 Dutt S, Deng W. Cluster-aware iterative improvement techniques for partitioning large VLSI circuits Acm Transactions On Design Automation of Electronic Systems. 7: 91-121. DOI: 10.1145/504914.504918  0.348
2001 Verma V, Dutt S. A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 144-151. DOI: 10.1145/605440.605449  0.347
2001 Mahapatra NR, Dutt S. Hardware-efficient and highly reconfigurable 4- and 2-track fault-tolerant designs for mesh-connected arrays Journal of Parallel and Distributed Computing. 61: 1391-1411. DOI: 10.1006/Jpdc.2001.1702  0.351
2000 Dutt S, Deng W. Probability-based approaches to VLSI circuit partitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 534-549. DOI: 10.1109/43.845078  0.388
1999 Dutt S, Arslan H, Theny H. Partitioning using second-order information and stochastic-gain functions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 421-435. DOI: 10.1109/43.752926  0.345
1998 Hanchek F, Dutt S. Methodologies for tolerating cell and interconnect faults in FPGAs Ieee Transactions On Computers. 47: 15-33. DOI: 10.1109/12.656073  0.361
1997 Dutt S, Hanchek F. REMOD: A new methodology for designing fault-tolerant arithmetic circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 5: 34-56. DOI: 10.1109/92.555985  0.376
1997 Mahapatra NR, Dutt S. Scalable global and local hashing strategies for duplicate pruning in parallel A* graph search Ieee Transactions On Parallel and Distributed Systems. 8: 738-756. DOI: 10.1109/71.598348  0.363
1997 Dutt S, Mahapatra NR. Node-covering, error-correcting codes and multiprocessors with very high average fault tolerance Ieee Transactions On Computers. 46: 997-1015. DOI: 10.1109/12.620481  0.371
1997 Dutt S, Hayes JP. A Local-Sparing Design Methodology for Fault-Tolerant Multiprocessors Computers and Mathematics With Applications. 34: 25-50. DOI: 10.1016/S0898-1221(97)00217-4  0.355
1996 Dutt S, Assaad FT. Mantissa-preserving operations and robust algorithm-based fault tolerance for matrix computations Ieee Transactions On Computers. 45: 408-424. DOI: 10.1109/12.494099  0.328
1994 Dutt S, Mahapatra NR. Scalable Load Balancing Strategies for Parallel A* Algorithms Journal of Parallel and Distributed Computing. 22: 488-505. DOI: 10.1006/Jpdc.1994.1106  0.348
1992 Dutt S, Hayes JP. Some Practical Issues in the Design of Fault-Tolerant Multiprocessors Ieee Transactions On Computers. 41: 588-598. DOI: 10.1109/12.142685  0.371
1991 Dutt S, Hayes JP. Subcube Allocation in Hypercube Computers Ieee Transactions On Computers. 40: 341-352. DOI: 10.1109/12.76413  0.331
1991 Dutt S, Hayes JP. Designing fault-tolerant systems using automorphisms Journal of Parallel and Distributed Computing. 12: 249-268. DOI: 10.1016/0743-7315(91)90129-W  0.354
1990 Dutt S, Hayes JP. On Designing and Reconfiguring K-Fault-Tolerant Tree Architectures Ieee Transactions On Computers. 39: 490-503. DOI: 10.1109/12.54842  0.323
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