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Javier A. Salcedo, Ph.D. - Publications

Affiliations: 
2006 University of Central Florida, Orlando, FL, United States 
Area:
Electronics and Electrical Engineering
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23 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 He L, Salcedo JA, Parthasarathy S, Hajjar J, Sundaram K. A New Low-Capacitance High-Voltage-Tolerant Protection Clamp for High-Speed Applications Ieee Transactions On Electron Devices. 67: 3030-3034. DOI: 10.1109/Ted.2020.3002877  0.577
2020 He L, Salcedo JA, Hajjar J, Sundaram K. Stacking Switch to Achieve Low-Trigger and High-Holding-Voltage-Clamp Characteristics Ieee Transactions On Electron Devices. 67: 1506-1510. DOI: 10.1109/Ted.2020.2971827  0.524
2019 Li H, Miao M, Zhou Y, Salcedo JA, Hajjar J, Sundaram KB. Modeling and Simulation of Comprehensive Diode Behavior Under Electrostatic Discharge Stresses Ieee Transactions On Device and Materials Reliability. 19: 90-96. DOI: 10.1109/Tdmr.2018.2882454  0.517
2018 He L, Salcedo JA, Parthasarathy S, Zhou Y, Hajjar J, Sundaram K. Compact and Fast-Response Voltage Clamp for Bi-Directional Signal Swing Interface Applications Ieee Electron Device Letters. 39: 1880-1883. DOI: 10.1109/Led.2018.2875714  0.493
2017 Dong A, Salcedo JA, Parthasarathy S, Zhou Y, Luo S, Hajjar J, Liou JJ. ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications Microelectronics Reliability. 79: 201-205. DOI: 10.1016/J.Microrel.2017.03.014  0.663
2016 Xi Y, Salcedo JA, Dong A, Liou JJ, Hajjar JJ. Robust Protection Device for Electrostatic Discharge/Electromagnetic Interference in Industrial Interface Applications Ieee Transactions On Device and Materials Reliability. 16: 263-265. DOI: 10.1109/Tdmr.2016.2530701  0.673
2016 Miao M, Zhou Y, Salcedo JA, Hajjar JJ, Liou JJ. A New Method to Estimate Failure Temperatures of Semiconductor Devices under Electrostatic Discharge Stresses Ieee Electron Device Letters. DOI: 10.1109/Led.2016.2608328  0.56
2015 Zhou Y, Miao M, Salcedo JA, Hajjar JJ, Liou JJ. Compact Thermal Failure Model for Devices Subject to Electrostatic Discharge Stresses Ieee Transactions On Electron Devices. 62: 4128-4134. DOI: 10.1109/Ted.2015.2491223  0.62
2015 Xi Y, Salcedo JA, Zhou Y, Liou JJ, Hajjar JJ. Design and characterization of ESD solutions with EMC robustness for automotive applications Microelectronics Reliability. DOI: 10.1016/J.Microrel.2015.09.018  0.573
2015 Miao M, Zhou Y, Salcedo JA, Hajjar JJ, Liou JJ. Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation Microelectronics Reliability. 55: 15-23. DOI: 10.1016/J.Microrel.2014.10.015  0.609
2014 Luo S, Salcedo JA, Parthasarathy S, Zhou Y, Hajjar JJ, Liou JJ. In situ ESD protection structure for variable operating voltage interface applications in 28-nm CMOS process Ieee Transactions On Device and Materials Reliability. 14: 1061-1067. DOI: 10.1109/Tdmr.2014.2364719  0.62
2014 Luo S, Salcedo JA, Hajjar JJ, Zhou Y, Liou JJ. A novel product-level human metal model characterization methodology Ieee Transactions On Device and Materials Reliability. 14: 772-774. DOI: 10.1109/Tdmr.2014.2311298  0.555
2014 Luo S, Salcedo JA, Hajjar JJ, Zhou Y, Liou JJ. ESD protection device with dual-polarity conduction and high blocking voltage realized in CMOS process Ieee Electron Device Letters. 35: 437-439. DOI: 10.1109/Led.2014.2305634  0.668
2014 Cui Q, Parthasarathy S, Salcedo JA, Liou JJ, Hajjar JJ, Zhou Y. Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications Microelectronics Reliability. 54: 57-63. DOI: 10.1016/J.Microrel.2013.09.021  0.634
2013 Cui Q, Salcedo JA, Parthasarathy S, Zhou Y, Liou JJ, Hajjar JJ. High-robustness and low-capacitance silicon-controlled rectifier for high-speed I/O ESD protection Ieee Electron Device Letters. 34: 178-180. DOI: 10.1109/Led.2012.2233708  0.575
2012 Malobabic S, Salcedo JA, Hajjar JJ, Liou JJ. NLDMOS ESD scaling under human metal model for 40-V mixed-signal applications Ieee Electron Device Letters. 33: 1595-1597. DOI: 10.1109/Led.2012.2213574  0.646
2012 Salcedo JA, Hajjar JJ, Malobabic S, Liou JJ. Bidirectional devices for automotive-grade electrostatic discharge applications Ieee Electron Device Letters. 33: 860-862. DOI: 10.1109/Led.2012.2190261  0.601
2012 Zhou Y(, Salcedo JA, Hajjar J. Modeling of high voltage devices for ESD event simulation in SPICE Microelectronics Journal. 43: 305-311. DOI: 10.1016/J.Mejo.2011.12.010  0.556
2011 Malobabic S, Salcedo JA, Righter AW, Hajjar JJ, Liou JJ. Correlation of human metal model and transmission line pulsing testing Ieee Electron Device Letters. 32: 1200-1202. DOI: 10.1109/Led.2011.2160141  0.601
2010 Malobabic S, Salcedo JA, Hajjar JJ, Liou JJ. Analysis of safe operating area of NLDMOS and PLDMOS transistors subject to transient stresses Ieee Transactions On Electron Devices. 57: 2655-2663. DOI: 10.1109/Ted.2010.2058310  0.643
2010 Ellis DF, Zhou Y, Salcedo JA, Hajjar JJ, Liou JJ. Prediction and modeling of thin gate oxide breakdown subject to arbitrary transient stresses Ieee Transactions On Electron Devices. 57: 2296-2305. DOI: 10.1109/Ted.2010.2053864  0.555
2010 Cui Q, Parthasarathy S, Salcedo JA, Liou JJ, Hajjar JJ, Zhou Y. Snapback and postsnapback saturation of pseudomorphic high-electron mobility transistor subject to transient overstress Ieee Electron Device Letters. 31: 425-427. DOI: 10.1109/Led.2010.2042029  0.576
2007 Salcedo JA, Liou JJ, Liu Z, Vinson JE. TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications Ieee Transactions On Electron Devices. 54: 822-832. DOI: 10.1109/Ted.2007.891251  0.503
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