☰

Jiang Hu, Ph.D. - Publications

Affiliations: 
2001 University of Minnesota, Twin Cities, Minneapolis, MN 
Area:
Electronics and Electrical Engineering
Tree Info Similar researchers PubMed Report error

59 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Zhuo C, Luo S, Gan H, Hu J, Shi Z. Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1498-1510. DOI: 10.1109/Tcad.2019.2917844  0.335
2019 Zhang GL, Li B, Shi Y, Hu J, Schlichtmann U. EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 705-718. DOI: 10.1109/Tcad.2018.2818713  0.388
2019 Snigdha FS, Sengupta D, Hu J, Sapatnekar SS. Dynamic Approximation of JPEG Hardware Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 295-308. DOI: 10.1109/Tcad.2018.2808224  0.344
2019 Sengupta D, Snigdha FS, Hu J, Sapatnekar SS. An Analytical Approach for Error PMF Characterization in Approximate Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 70-83. DOI: 10.1109/Tcad.2018.2803626  0.347
2018 Xu W, Sapatnekar SS, Hu J. A Simple Yet Efficient Accuracy-Configurable Adder Design Ieee Transactions On Very Large Scale Integration Systems. 26: 1112-1125. DOI: 10.1109/Tvlsi.2018.2803081  0.358
2018 Wang Y, Chen P, Hu J, Li G, Rajendran J. The Cat and Mouse in Split Manufacturing Ieee Transactions On Very Large Scale Integration Systems. 26: 805-817. DOI: 10.1109/Tvlsi.2017.2787754  0.343
2018 Lee S, Shi C, Wang J, Sanabria A, Osman H, Hu J, Sanchez-Sinencio E. A Built-In Self-Test and In Situ Analog Circuit Optimization Platform Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 3445-3458. DOI: 10.1109/Tcsi.2018.2805641  0.35
2016 Won JY, Gratz PV, Shakkottai S, Hu J. Resource sharing centric dynamic voltage and frequency scaling for CMP cores, uncore, and memory Acm Transactions On Design Automation of Electronic Systems. 21. DOI: 10.1145/2897394  0.329
2016 Silva-Martinez J, Karşılayan Aİ, Hu J, Krishnaswamy H. Special Issue on the 57th International Midwest Symposium on Circuits and Systems Analog Integrated Circuits and Signal Processing. 88: 181-183. DOI: 10.1007/S10470-016-0776-3  0.34
2015 Davoodi A, Hu J, Ozdal M, Sze CCN. Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 501. DOI: 10.1109/Tcad.2015.2410671  0.341
2014 Chen X, Hu J, Xu N. Regularity-constrained floorplanning for multi-core processors Integration. 47: 86-95. DOI: 10.1016/J.Vlsi.2013.05.002  0.381
2013 Chen X, Xu Z, Kim H, Gratz P, Hu J, Kishinevsky M, Ogras U. In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches Acm Transactions On Design Automation of Electronic Systems. 18: 1-21. DOI: 10.1145/2504905  0.324
2013 Shim K, Hu J. Boostable Repeater Design for Variation Resilience in VLSI Interconnects Ieee Transactions On Very Large Scale Integration Systems. 21: 1619-1631. DOI: 10.1109/Tvlsi.2012.2212733  0.373
2013 Shim KN, Hu J, Silva-Martinez J. Dual-level adaptive supply voltage system for variation resilience Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1041-1052. DOI: 10.1109/Tvlsi.2012.2203326  0.357
2013 Hu J, Koh CK. Guest editorial: Special section on cross-domain physical optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 173-174. DOI: 10.1109/Tcad.2013.2238475  0.384
2012 Ozdal MM, Burns S, Hu J. Algorithms for gate sizing and device parameter selection for high-performance designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1558-1571. DOI: 10.1109/Tcad.2012.2196279  0.449
2011 Chaudhry MAR, Asad Z, Sprintson A, Hu J. Efficient congestion mitigation using congestion-aware steiner trees and network coding topologies Vlsi Design. 2011. DOI: 10.1155/2011/892310  0.395
2011 Liu Y, Hu J. GPU-Based Parallelization for Fast Circuit Optimization Acm Transactions On Design Automation of Electronic Systems. 16: 24. DOI: 10.1145/1970353.1970357  0.39
2011 Liu Y, Shelar RS, Hu J. Simultaneous technology mapping and placement for delay minimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 416-426. DOI: 10.1109/Tcad.2010.2089569  0.734
2010 Shen W, Cai Y, Hong X, Hu J. An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement Ieee Transactions On Very Large Scale Integration Systems. 18: 1639-1648. DOI: 10.1109/Tvlsi.2009.2030156  0.385
2010 Samanta R, Hu J, Li P. Discrete buffer and wire sizing for link-based non-tree clock networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1025-1035. DOI: 10.1109/Tvlsi.2009.2019088  0.399
2010 Hu S, Shah P, Hu J. Pattern Sensitive Placement Perturbation for Manufacturability Ieee Transactions On Very Large Scale Integration Systems. 18: 1002-1006. DOI: 10.1109/Tvlsi.2009.2017268  0.399
2010 Venkataraman G, Feng Z, Hu J, Li P. Combinatorial algorithms for fast clock mesh optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 131-141. DOI: 10.1109/Tvlsi.2008.2007737  0.443
2010 Ye X, Li P, Zhao M, Panda R, Hu J. Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1342-1353. DOI: 10.1109/Tcad.2010.2059090  0.385
2010 Liu Y, Hu J. A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 223-234. DOI: 10.1109/Tcad.2009.2035575  0.442
2009 Samanta R, Venkataraman G, Hu J. Clock buffer polarity assignment for power noise reduction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 770-780. DOI: 10.1109/Tvlsi.2008.2009187  0.381
2009 Liu Y, Zhang T, Hu J. Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations Ieee Transactions On Very Large Scale Integration Systems. 17: 439-443. DOI: 10.1109/Tvlsi.2008.2004545  0.328
2009 Hu S, Ketkar M, Hu J. Gate Sizing for Cell-Library-Based Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 818-825. DOI: 10.1109/Tcad.2009.2015735  0.445
2009 Hu S, Hu J. A fast general slew constrained minimum cost buffering algorithm Microelectronics Journal. 40: 1482-1486. DOI: 10.1016/J.Mejo.2009.08.003  0.438
2009 Shen W, Cai Y, Hong X, Hu J, Lu B. A single layer zero skew clock routing in X architecture Science in China Series F: Information Sciences. 52: 1466-1475. DOI: 10.1007/S11432-009-0028-6  0.421
2008 Padmanabhan U, Wang JM, Hu J. Robust Clock Tree Routing in the Presence of Process Variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1385-1397. DOI: 10.1109/Tcad.2008.925776  0.442
2008 Zhuo C, Hu J, Zhao M, Chen K. Power Grid Analysis and Optimization Using Algebraic Multigrid Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 738-751. DOI: 10.1109/Tcad.2008.917587  0.389
2008 Liu Y, Hu J, Shi W. Buffering Interconnect for Multicore Processor Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2183-2196. DOI: 10.1109/Tcad.2008.2006149  0.435
2008 Shen W, Cai Y, Hong X, Hu J. Low Power Gated Clock Tree Driven Placement Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 91: 595-603. DOI: 10.1093/Ietfec/E91-A.2.595  0.367
2008 Cao K, Hu J. ASIC design flow considering lithography-induced effects Iet Circuits, Devices and Systems. 2: 23-29. DOI: 10.1049/Iet-Cds:20070112  0.376
2008 Shen W, Cai Y, Hong X, Hu J, Lu B. Zero skew clock routing in X-architecture based on an improved greedy matching algorithm Integration. 41: 426-438. DOI: 10.1016/J.Vlsi.2007.10.004  0.449
2007 Cao K, Hu J, Cheng M. Wire sizing and spacing for lithographic printability optimization Proceedings of Spie - the International Society For Optical Engineering. 6521. DOI: 10.1117/12.708974  0.422
2007 Cao K, Hu J, Cheng M. Wire Sizing and Spacing for Lithographic Printability and Timing Optimization Ieee Transactions On Very Large Scale Integration Systems. 15: 1332-1340. DOI: 10.1109/Tvlsi.2007.909807  0.442
2007 Hu S, Li Q, Hu J, Li P. Utilizing Redundancy for Timing Critical Interconnect Ieee Transactions On Very Large Scale Integration Systems. 15: 1067-1080. DOI: 10.1109/Tvlsi.2007.903911  0.401
2007 Venkataraman G, Hu J, Liu F. Integrated placement and skew optimization for rotary clocking Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 149-157. DOI: 10.1109/Tvlsi.2007.893577  0.428
2007 Hu S, Alpert CJ, Hu J, Karandikar SK, Li Z, Shi W, Sze CN. Fast algorithms for slew-constrained minimum cost buffering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2009-2022. DOI: 10.1109/Tcad.2007.906477  0.738
2007 Su B, Chang Y, Hu J. An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 719-733. DOI: 10.1109/Tcad.2007.892338  0.369
2007 Sze CN, Alpert CJ, Hu J, Shi W. Path-Based Buffer Insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1346-1355. DOI: 10.1109/Tcad.2006.888281  0.44
2006 Wu D, Hu J, Mahapatra RN. Antenna avoidance in layer assignment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 734-738. DOI: 10.1109/Tcad.2006.870061  0.364
2006 Rajaram A, Hu J, Mahapatra R. Reducing clock skew variability via crosslinks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1176-1182. DOI: 10.1109/Tcad.2005.855928  0.381
2006 Alpert CJ, Hu J, Sapatnekar SS, Sze CN. Accurate estimation of global buffer delay within a floorplan Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1140-1145. DOI: 10.1109/Tcad.2005.855889  0.384
2005 Young K, Frodsham A, Doumbo OK, Gupta S, Dolo A, Hu JT, Robson KJ, Crisanti A, Hill AV, Gilbert SC. Inverse associations of human leukocyte antigen and malaria parasite types in two West African populations. Infection and Immunity. 73: 953-5. PMID 15664937 DOI: 10.1128/IAI.73.2.953-955.2005  0.387
2005 Chaturvedi R, Hu J. An efficient merging scheme for prescribed skew clock routing Ieee Transactions On Very Large Scale Integration Systems. 13: 750-754. DOI: 10.1109/Tvlsi.2005.848821  0.397
2005 Lu Y, Sze C, Hong X, Zhou Q, Cai Y, Huang L, Hu J. Navigating Register Placement for Low Power Clock Network Design*This work was supported by Hi-Tech Research & Development (863) Program of China 2002AA1Z1460, the National Natural Science Foundation of China (NSFC) 60476014, Specialized Research Fund for the Doctoral Program of Higher Education: SRFDP-20020003008 and DAC Graduate Scholarship. Some preliminary results of this paper was presented at Asia South Pacific Design Automation Conference (ASPDAC), January, 2005 [17]. Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 88: 3405-3411. DOI: 10.1093/Ietfec/E88-A.12.3405  0.383
2004 Su H, Hu J, Sapatnekar SS, Nassif SR. A methodology for the simultaneous design of supply and signal networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1614-1624. DOI: 10.1109/Tcad.2004.837728  0.593
2004 Alpert CJ, Gandham G, Hrkic M, Hu J, Quay ST, Sze CN. Porosity-aware buffered Steiner tree construction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 517-526. DOI: 10.1109/Tcad.2004.825864  0.408
2004 Alpert C, Chu C, Gandham G, Hrkic M, Hu J, Kashyap C, Quay S. Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 136-141. DOI: 10.1109/Tcad.2003.819910  0.381
2003 Alpert CJ, Hu J, Sapatnekar SS, Villarrubia PG. A practical methodology for early buffer and wire resource allocation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 573-583. DOI: 10.1109/Tcad.2003.810749  0.388
2003 Hu J, Alpert CJ, Quay ST, Gandham G. Buffer insertion with adaptive blockage avoidance Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 492-498. DOI: 10.1109/Tcad.2003.809647  0.402
2002 Hu J, Sapatnekar SS. A timing-constrained simultaneous global routing algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1025-1036. DOI: 10.1109/Tcad.2002.801083  0.629
2001 Alpert CJ, Gandham G, Hu J, Neves JL, Quay ST, Sapatnekar SS. Steiner tree optimization for buffers, blockages, and bays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 556-562. DOI: 10.1109/43.918213  0.414
2001 Hu J, Sapatnekar SS. Performance driven global routing through gradual refinement Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 481-483. DOI: 10.1080/1065514021000012219  0.603
2001 Hu J, Sapatnekar SS. A survey on multi-net global routing for integrated circuits Integration, the Vlsi Journal. 31: 1-49. DOI: 10.1016/S0167-9260(01)00020-7  0.579
2000 Hu J, Sapatnekar SS. Algorithms for non-hanan-based optimization for VLSI interconnect under a higher-order AWE model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 446-458. DOI: 10.1109/43.838994  0.617
Show low-probability matches.