| Year |
Citation |
Score |
| 2013 |
Gavin P, Whalley D, Själander M. Reducing instruction fetch energy in multi-issue processors Transactions On Architecture and Code Optimization. 10. DOI: 10.1145/2541228.2555318 |
0.382 |
|
| 2013 |
Bardizbanyan A, Själander M, Whalley D, Larsson-Edefors P. Designing a practical Data Filter Cache to improve both energy efficiency and performance Transactions On Architecture and Code Optimization. 10. DOI: 10.1145/2541228.2555310 |
0.319 |
|
| 2012 |
Finlayson I, Uh GR, Whalley DB, Tyson G. An overview of static pipelining Ieee Computer Architecture Letters. 11: 17-20. DOI: 10.1109/L-Ca.2011.26 |
0.724 |
|
| 2010 |
Mohan S, Mueller F, Root M, Hawkins W, Healy C, Whalley D, Vivancos E. Parametric timing analysis and its application to dynamic voltage scaling Acm Transactions in Embedded Computing Systems. 10: 25. DOI: 10.1145/1880050.1880061 |
0.362 |
|
| 2009 |
Whalley D. Session details: Scheduling Sigplan Notices. 44. DOI: 10.1145/3263669 |
0.31 |
|
| 2008 |
Wilhelm R, Engblom J, Ermedahl A, Holsti N, Thesing S, Whalley D, Bernat G, Ferdinand C, Heckmann R, Mitra T, Mueller F, Puaut I, Puschner P, Staschulat J, Stenström P. The worst-case execution-time problem—overview of methods and survey of tools Acm Transactions in Embedded Computing Systems. 7: 36. DOI: 10.1145/1347375.1347389 |
0.361 |
|
| 2007 |
Hines S, Tyson G, Whalley D. Addressing instruction fetch bottlenecks by using an instruction register file Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes). 165-174. DOI: 10.1145/1254766.1254800 |
0.32 |
|
| 2006 |
Kulkarni P, Zhao W, Hines S, Whalley D, Yuan X, Engelen Rv, Gallivan K, Hiser J, Davidson J, Cai B, Bailey M, Moon H, Cho K, Paek Y. VISTA Acm Transactions On Embedded Computing Systems. 5: 819-863. DOI: 10.1145/1196636.1196640 |
0.604 |
|
| 2006 |
Hines S, Whalley D, Tyson G. Adapting compilation techniques to enhance the packing of instructions into registers Cases 2006: International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 43-53. DOI: 10.1145/1176760.1176768 |
0.423 |
|
| 2006 |
Zhao W, Kreahling W, Whalley D, Healy C, Mueller F. Improving WCET by applying worst-case path optimizations Real-Time Systems. 34: 129-152. DOI: 10.1007/S11241-006-8643-4 |
0.619 |
|
| 2005 |
Zhao W, Whalley D, Healy C, Mueller F. Improving WCET by applying a WC code-positioning optimization Acm Transactions On Architecture and Code Optimization. 2: 335-365. DOI: 10.1145/1113841.1113842 |
0.6 |
|
| 2005 |
Hines S, Tyson G, Whalley D. Reducing instruction fetch cost by packing instructions into register windows Proceedings of the Annual International Symposium On Microarchitecture, Micro. 19-29. DOI: 10.1109/MICRO.2005.27 |
0.307 |
|
| 2005 |
Whaley RC, Whalley DB. Tuning high performance kernels through empirical compilation Proceedings of the International Conference On Parallel Processing. 2005: 89-98. DOI: 10.1109/ICPP.2005.77 |
0.704 |
|
| 2005 |
Uh GR, Wang Y, Whalley D, Jinturkar S, Paek Y, Cao V, Burns C. Compiler transformations for effectively exploiting a zero overhead loop buffer Software - Practice and Experience. 35: 393-412. DOI: 10.1002/Spe.642 |
0.451 |
|
| 2005 |
Kreahling WC, Whalley D, Bailey MW, Yuan X, Uh GR, Van Engelen R. Branch elimination by condition merging Software - Practice and Experience. 35: 51-74. DOI: 10.1002/Spe.627 |
0.611 |
|
| 2004 |
Cho J, Paek Y, Whalley D. Fast Memory Bank Assignment for Fixed-Point Digital Signal Processors Acm Transactions On Design Automation of Electronic Systems. 9: 52-74. DOI: 10.1145/966137.966140 |
0.403 |
|
| 2004 |
Van Engelen R, Whalley D, Yuan X. Automatic validation of code-improving transformations on low-level program representations Science of Computer Programming. 52: 257-280. DOI: 10.1016/J.Scico.2004.03.008 |
0.343 |
|
| 2003 |
Whalley D. Session details: Partitioning and memory optimizations Sigplan Notices. 38. DOI: 10.1145/3262143 |
0.362 |
|
| 2002 |
Healy CA, Whalley DB. Automatic detection and exploitation of branch constraints for timing analysis Ieee Transactions On Software Engineering. 28: 763-781. DOI: 10.1109/TSE.2002.1027799 |
0.31 |
|
| 2001 |
Mellor-Crummey J, Whalley D, Kennedy K. Improving Memory Hierarchy Performance for Irregular Applications Using Data and Computation Reorderings International Journal of Parallel Programming. 29: 217-247. DOI: 10.1023/A:1011119519789 |
0.365 |
|
| 2001 |
Mellor-Crummey J, Fowler R, Whalley D. Tools for application-oriented performance tuning Proceedings of the International Conference On Supercomputing. 154-165. |
0.302 |
|
| 1999 |
White RT, Mueller F, Healy C, Whalley D, Harmon M. Timing Analysis for Data and Wrap-Around Fill Caches Real-Time Systems. 17: 209-233. DOI: 10.1023/A:1008190423977 |
0.452 |
|
| 1999 |
Uh GR, Whalley DB. Effectively exploiting indirect jumps Software - Practice and Experience. 29: 1061-1101. DOI: 10.1002/(SICI)1097-024X(199910)29:12<1061::AID-SPE272>3.0.CO;2-K |
0.391 |
|
| 1999 |
Ko L, Al-Yaqoubi N, Healy C, Ratliff E, Arnold R, Whalley D, Harmon M. Timing constraint specification and analysis Software - Practice and Experience. 29: 77-98. DOI: 10.1002/(Sici)1097-024X(199901)29:1<77::Aid-Spe222>3.3.Co;2-V |
0.359 |
|
| 1995 |
Mueller F, Whalley DB. Avoiding Conditional Branches by Code Replication Acm Sigplan Notices. 30: 56-66. DOI: 10.1145/223428.207116 |
0.431 |
|
| 1994 |
Arnold R, Mueller F, Whalley D, Harmon M. Bounding worst-case instruction cache performance Proceedings - Real-Time Systems Symposium. 172-181. DOI: 10.1109/REAL.1994.342718 |
0.337 |
|
| 1993 |
Boyd MR, Whalley DB. Isolation and Analysis of Optimization Errors Acm Sigplan Notices. 28: 26-35. DOI: 10.1145/173262.155093 |
0.343 |
|
| 1992 |
Mueller F, Whalley DB. Avoiding Unconditional Jumps by Code Replication Acm Sigplan Notices. 27: 322-330. DOI: 10.1145/143103.143144 |
0.389 |
|
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