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Chaitali Chakrabarti - Publications

Affiliations: 
Arizona State University, Tempe, AZ, United States 
Area:
Electronics and Electrical Engineering, Computer Science
Website:
https://search.asu.edu/profile/22557
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129 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 West BL, Zhou J, Dreslinksi RG, Kripfgans OD, Fowlkes JB, Chakrabarti C, Wenisch TF. Tetris : Using Software/Hardware Co-Design to Enable Handheld, Physics-Limited 3D Plane-Wave Ultrasound Imaging Ieee Transactions On Computers. 69: 1209-1220. DOI: 10.1109/Tc.2020.2990061  0.37
2020 Krishnan G, Mandal SK, Chakrabarti C, Seo Js, Ogras UY, Cao Y. Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs Ieee Design & Test of Computers. 1-1. DOI: 10.1109/Mdat.2020.3001559  0.351
2020 Kadetotad D, Yin S, Berisha V, Chakrabarti C, Seo J. An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition Ieee Journal of Solid-State Circuits. 55: 1877-1887. DOI: 10.1109/Jssc.2020.2992900  0.448
2020 Park D, Pal S, Feng S, Gao P, Tan J, Rovinski A, Xie S, Zhao C, Amarnath A, Wesley T, Beaumont J, Chen K, Chakrabarti C, Taylor MB, Mudge T, et al. A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator Ieee Journal of Solid-State Circuits. 55: 933-944. DOI: 10.1109/Jssc.2019.2960480  0.412
2020 Mandal SK, Krishnan G, Chakrabarti C, Seo J, Cao Y, Ogras UY. A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1-1. DOI: 10.1109/Jetcas.2020.3015509  0.327
2020 Zhou J, Papandreou-Suppappola A, Chakrabarti C. Parallel Gibbs Sampler for Wavelet-Based Bayesian Compressive Sensing with High Reconstruction Accuracy Journal of Signal Processing Systems. 92: 1101-1114. DOI: 10.1007/S11265-020-01541-2  0.626
2019 Li Z, Xiang J, Gong L, Blaauw D, Chakrabarti C, Kim HS. Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low-Power Mobile Vision Applications Ieee Transactions On Circuits and Systems For Video Technology. 29: 2191-2204. DOI: 10.1109/Tcsvt.2018.2854284  0.436
2019 Chen H, Lee S, Mudge T, Wu C, Chakrabarti C. Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems Ieee Transactions On Computers. 68: 646-659. DOI: 10.1109/Tc.2018.2886884  0.454
2019 Gupta U, Mandal SK, Mao M, Chakrabarti C, Ogras UY. A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors Ieee Computer Architecture Letters. 18: 14-17. DOI: 10.1109/Lca.2019.2892151  0.323
2019 Mao M, Peng X, Liu R, Li J, Yu S, Chakrabarti C. MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 9: 398-410. DOI: 10.1109/Jetcas.2019.2908937  0.422
2018 Zhou J, Wei S, Jintamethasawat R, Sampson R, Kripfgans OD, Fowlkes JB, Wenisch TF, Chakrabarti C. High Volume-Rate 3D Ultrasound Imaging based on Synthetic Aperture Sequential Beamforming with Chirp-Coded Excitation. Ieee Transactions On Ultrasonics, Ferroelectrics, and Frequency Control. PMID 29994304 DOI: 10.1109/Tuffc.2018.2839085  0.337
2018 Jintamethasawat R, Lee WM, Carson PL, Hooi FM, Fowlkes JB, Goodsitt MM, Sampson R, Wenisch TF, Wei S, Zhou J, Chakrabarti C, Kripfgans OD. Error analysis of speed of sound reconstruction in ultrasound limited angle transmission tomography. Ultrasonics. 88: 174-184. PMID 29674228 DOI: 10.1016/J.Ultras.2018.03.016  0.326
2018 Mao M, Yu S, Chakrabarti C. Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1290-1300. DOI: 10.1109/Tvlsi.2018.2814544  0.407
2017 Wei S, Yang M, Zhou J, Sampson R, Kripfgans O, Fowlkes B, Wenisch T, Chakrabarti C. Low Cost 3D Flow Estimation of Blood with Clutter. Ieee Transactions On Ultrasonics, Ferroelectrics, and Frequency Control. PMID 28362605 DOI: 10.1109/Tuffc.2017.2676091  0.322
2017 Mao M, Chen P, Yu S, Chakrabarti C. A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 1611-1621. DOI: 10.1109/Tvlsi.2017.2651647  0.446
2016 Chen H, Wu C, Mudge T, Chakrabarti C. RATT-ECC Acm Transactions On Architecture and Code Optimization. 13: 1-24. DOI: 10.1145/2957758  0.377
2016 Chen H, Jeloka S, Arunkumar A, Blaauw D, Wu C, Mudge T, Chakrabarti C. Using Low Cost Erasure and Error Correction Schemes to Improve Reliability of Commodity DRAM Systems Ieee Transactions On Computers. 65: 3766-3779. DOI: 10.1109/Tc.2016.2550455  0.406
2016 Mao M, Cao Y, Yu S, Chakrabarti C. Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2547745  0.473
2015 Chen HM, Arunkumar A, Wu CJ, Mudge T, Chakrabarti C. E-ECC: Low power erasure and error correction schemes for increasing reliability of commodity DRAM systems Acm International Conference Proceeding Series. 5: 60-70. DOI: 10.1145/2818950.2818961  0.348
2015 Yang M, Sampson R, Wei S, Wenisch TF, Chakrabarti C. Separable beamforming for 3-D medical ultrasound imaging Ieee Transactions On Signal Processing. 63: 279-290. DOI: 10.1109/Tsp.2014.2371772  0.38
2015 Mao M, Cao Y, Yu S, Chakrabarti C. Programming strategies to improve energy efficiency and reliability of ReRAM memory systems Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2015. DOI: 10.1109/SiPS.2015.7344980  0.362
2015 Mao M, Cao Y, Yu S, Chakrabarti C. Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings Proceedings of the 33rd Ieee International Conference On Computer Design, Iccd 2015. 359-366. DOI: 10.1109/ICCD.2015.7357125  0.311
2015 Banavar MK, Zhang JJ, Chakraborty B, Kwon H, Li Y, Jiang H, Spanias A, Tepedelenlioglu C, Chakrabarti C, Papandreou-Suppappola A. An overview of recent advances on distributed and agile sensing algorithms and implementation Digital Signal Processing: a Review Journal. 39: 1-14. DOI: 10.1016/J.Dsp.2015.01.001  0.567
2014 Xu Q, Varadarajan S, Chakrabarti C, Karam LJ. A distributed Canny edge detector: algorithm and FPGA implementation. Ieee Transactions On Image Processing : a Publication of the Ieee Signal Processing Society. 23: 2944-60. PMID 24983098 DOI: 10.1109/Tip.2014.2311656  0.405
2014 Mao M, Yang C, Xu Z, Cao Y, Chakrabarti C. Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. DOI: 10.1109/SiPS.2014.6986076  0.335
2014 Sampson R, Yang M, Wei S, Chakrabarti C, Wenisch TF. Sonic millip3De: An architecture for handheld 3D ultrasound Ieee Micro. 34: 100-108. DOI: 10.1109/Mm.2014.49  0.333
2014 Xu Z, Yang C, Mao M, Sutaria KB, Chakrabarti C, Cao Y. Compact modeling of STT-MTJ devices Solid-State Electronics. 102: 76-81. DOI: 10.1016/J.Sse.2014.06.003  0.606
2014 Yang C, Chen HM, Mudge TN, Chakrabarti C. Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding Journal of Signal Processing Systems. 1-10. DOI: 10.1007/s11265-014-0880-5  0.325
2014 Yang C, Emre Y, Xu Z, Chen H, Cao Y, Chakrabarti C. A low cost multi-tiered approach to improving the reliability of multi-level cell pram Journal of Signal Processing Systems. 76: 133-147. DOI: 10.1007/s11265-013-0856-x  0.701
2013 Giridhar B, Cieslak M, Duggal D, Dreslinski R, Chen HM, Patti R, Hold B, Chakrabarti C, Mudge T, Blaauw D. Exploring DRAM organizations for energy-efficient and resilient exascale memories International Conference For High Performance Computing, Networking, Storage and Analysis, Sc. DOI: 10.1145/2503210.2503215  0.331
2013 Emre Y, Chakrabarti C. Techniques for compensating memory errors in JPEG2000 Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 159-163. DOI: 10.1109/Tvlsi.2011.2180407  0.72
2013 Miao L, Zhang JJ, Chakrabarti C, Papandreou-Suppappola A. Efficient bayesian tracking of multiple sources of neural activity: Algorithms and real-time FPGA implementation Ieee Transactions On Signal Processing. 61: 633-647. DOI: 10.1109/Tsp.2012.2226172  0.714
2013 Emre Y, Chakrabarti C. Energy and quality-aware multimedia signal processing Ieee Transactions On Multimedia. 15: 1579-1593. DOI: 10.1109/Tmm.2013.2266094  0.687
2013 Zheng Q, Chen Y, Dreslinski R, Chakrabarti C, Anastasopoulos A, Mahlke S, Mudge T. Parallelization techniques for implementing trellis algorithms on graphics processors Proceedings - Ieee International Symposium On Circuits and Systems. 1220-1223. DOI: 10.1109/ISCAS.2013.6572072  0.354
2013 Yang C, Muckatira D, Kulkarni A, Chakrabarti C. Data storage time sensitive ECC schemes for MLC NAND Flash memories Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2513-2517. DOI: 10.1109/ICASSP.2013.6638108  0.306
2013 Miao L, Michael S, Kovvali N, Chakrabarti C, Papandreou-Suppappola A. Multi-source neural activity estimation and sensor scheduling: Algorithms and hardware implementation Journal of Signal Processing Systems. 70: 145-162. DOI: 10.1007/s11265-012-0701-7  0.583
2013 Miao L, Chakrabarti C. A parallel stochastic computing system with improved accuracy Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 195-200.  0.569
2012 Yang C, Emre Y, Cao Y, Chakrabarti C. Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding Eurasip Journal On Advances in Signal Processing. 2012. DOI: 10.1186/1687-6180-2012-211  0.756
2012 Yang C, Emre Y, Chakrabarti C. Product code schemes for error correction in MLC NAND flash memories Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 2302-2314. DOI: 10.1109/Tvlsi.2011.2174389  0.746
2012 Yang C, Emre Y, Cao Y, Chakrabarti C. Multi-tiered approach to improving the reliability of multi-level cell pram Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 114-119. DOI: 10.1109/SiPS.2012.46  0.675
2012 Emre Y, Yang C, Sutaria K, Cao Y, Chakrabarti C. Enhancing the reliability of STT-RAM through circuit and system level techniques Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 125-130. DOI: 10.1109/SiPS.2012.11  0.673
2012 Jeon D, Seok M, Chakrabarti C, Blaauw D, Sylvester D. A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS Ieee Journal of Solid-State Circuits. 47: 23-34. DOI: 10.1109/Jssc.2011.2169311  0.439
2012 Yu CL, Chakrabarti C. Transpose-free SAR imaging on FPGA platform Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 762-765. DOI: 10.1109/ISCAS.2012.6272149  0.359
2012 Maurer A, Miao L, Zhang JJ, Kovvali N, Papandreou-Suppappola A, Chakrabarti C. EEG/MEG artifact suppression for improved neural activity estimation Conference Record - Asilomar Conference On Signals, Systems and Computers. 1646-1650. DOI: 10.1109/ACSSC.2012.6489311  0.509
2012 Emre Y, Chakrabarti C. Quality-aware techniques for reducing power of JPEG codecs Journal of Signal Processing Systems. 69: 227-237. DOI: 10.1007/s11265-012-0667-5  0.674
2012 Qi Q, Chakrabarti C. Parallel high throughput soft-output sphere Decoding Algorithm Journal of Signal Processing Systems. 68: 217-231. DOI: 10.1007/s11265-011-0602-1  0.534
2011 Jain A, Shrivastava A, Chakrabarti C. LA-LRU: A latency-aware replacement policy for variation tolerant caches Proceedings of the Ieee International Conference On Vlsi Design. 298-303. DOI: 10.1109/VLSID.2011.24  0.316
2011 Yu CL, Irick K, Chakrabarti C, Narayanan V. Multidimensional DFT IP generator for FPGA platforms Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 755-764. DOI: 10.1109/Tcsi.2010.2078750  0.653
2011 Miao L, Zhang JJ, Chakrabarti C, Papandreou-Suppappola A, Kovvali N. Real-time closed-loop tracking of an unknown number of neural sources using probability hypothesis density particle filtering 2011 Ieee Workshop On Signal Processing Systems, Sips 2011, Proceedings. 367-372. DOI: 10.1109/SiPS.2011.6089004  0.562
2011 Yang C, Emre Y, Chakrabarti C, Mudge T. Flexible product code-based ECC schemes for MLC NAND Flash memories 2011 Ieee Workshop On Signal Processing Systems, Sips 2011, Proceedings. 255-260. DOI: 10.1109/SiPS.2011.6088985  0.665
2011 Jeon D, Seok M, Chakrabarti C, Blaauw D, Sylvester D. Energy-optimized high performance FFT processor Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1701-1704. DOI: 10.1109/ICASSP.2011.5946828  0.365
2011 Emre Y, Chakrabarti C. Data-path and memory error compensation technique for low power JPEG implementation Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1589-1592. DOI: 10.1109/ICASSP.2011.5946800  0.686
2011 Xu Q, Chakrabarti C, Karam LJ. A distributed Canny edge detector and its implementation on FPGA 2011 Digital Signal Processing and Signal Processing Education Meeting, Dsp/Spe 2011 - Proceedings. 500-505. DOI: 10.1109/DSP-SPE.2011.5739265  0.312
2011 Emre Y, Chakrabarti C. Low energy motion estimation via selective aproximations Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 176-183. DOI: 10.1109/ASAP.2011.6043266  0.655
2011 DeBole M, Xiao Y, Yu CL, Al Maashri A, Cotter M, Chakrabarti C, Narayanan V. FPGA-accelerator system for computing biologically inspired feature extraction models Conference Record - Asilomar Conference On Signals, Systems and Computers. 751-755. DOI: 10.1109/ACSSC.2011.6190106  0.301
2011 Yu CL, Kim JS, Deng L, Kestur S, Narayanan V, Chakrabarti C. FPGA architecture for 2d discrete Fourier transform based on 2d decomposition for large-sized data Journal of Signal Processing Systems. 64: 109-122. DOI: 10.1007/s11265-010-0500-y  0.334
2010 Lee H, Chakrabarti C, Mudge T. A low-power DSP for wireless communications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1310-1322. DOI: 10.1109/Tvlsi.2009.2023547  0.447
2010 Miao L, Zhang JJ, Chakrabarti C, Papandreou-Suppappola A. A new parallel implementation for particle filters and its application to adaptive waveform design Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 19-24. DOI: 10.1109/SIPS.2010.5624820  0.61
2010 Qi Q, Chakrabarti C. Parallel high throughput soft-output sphere decoder Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 174-179. DOI: 10.1109/SIPS.2010.5624783  0.516
2010 Emre Y, Chakrabarti C. Memory error compensation techniques for JPEG2000 Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 36-41. DOI: 10.1109/SIPS.2010.5624759  0.696
2010 Woh M, Seo S, Mahlke S, Mudge T, Chakrabarti C, Flautner K. AnySP: Anytime anywhere anyway signal processing Ieee Micro. 30: 81-91. DOI: 10.1109/Mm.2010.8  0.355
2010 Woh M, Mahlke S, Mudge T, Chakrabarti C. Mobile supercomputers for the next-generation cell phone Computer. 43: 81-85. DOI: 10.1109/Mc.2010.16  0.374
2010 Emre Y, Chakrabarti C. Energy-aware adaptive OFDM systems Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1590-1593. DOI: 10.1109/ICASSP.2010.5495534  0.632
2010 Yu CL, Chakrabarti C, Park S, Narayanan V. Bandwidth-intensive FPGA architecture for multi-dimensional DFT Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1486-1489. DOI: 10.1109/ICASSP.2010.5495495  0.344
2010 Woh M, Seo S, Chakrabarti C, Mahlke S, Mudge T. An ultra low power SIMD processor for wireless devices Conference Record - Asilomar Conference On Signals, Systems and Computers. 390-394. DOI: 10.1109/ACSSC.2010.5757542  0.383
2010 Edla S, Zhang JJ, Spanias J, Kovvali N, Papandreou-Suppappola A, Chakrabarti C. Adaptive parameter estimation of cardiovascular signals using sequential Bayesian techniques Conference Record - Asilomar Conference On Signals, Systems and Computers. 374-378. DOI: 10.1109/ACSSC.2010.5757538  0.492
2010 Miao L, Zhang JJ, Chakrabarti C, Papandreou-Suppappola A. Multiple sensor sequential tracking of neural activity: Algorithm and FPGA implementation Conference Record - Asilomar Conference On Signals, Systems and Computers. 369-373. DOI: 10.1109/ACSSC.2010.5757537  0.586
2009 Papirla V, Jain A, Chakrabarti C. Low power robust signal processing Proceedings of the International Symposium On Low Power Electronics and Design. 303-306. DOI: 10.1145/1594233.1594308  0.309
2009 Deng L, Chakrabarti C, Pitsianis N, Sun X. Automated optimization of look-up table implementation for function evaluation on FPGAs Proceedings of Spie - the International Society For Optical Engineering. 7444. DOI: 10.1117/12.834184  0.364
2009 Li Y, Reisslein M, Chakrabarti C. Energy-efficient video transmission over a wireless link Ieee Transactions On Vehicular Technology. 58: 1229-1244. DOI: 10.1109/Tvt.2008.927720  0.405
2009 Zhuo J, Chakrabarti C, Lee K, Chang N, Vrudhula S. Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 22-32. DOI: 10.1109/Tvlsi.2008.2008432  0.406
2009 Zhu Y, Chakrabarti C. Architecture-aware LDPC code design for multiprocessor software defined radio systems Ieee Transactions On Signal Processing. 57: 3679-3692. DOI: 10.1109/Tsp.2009.2022356  0.441
2009 Banerjee N, Karakonstantis G, Choi JH, Chakrabarti C, Roy K. Design methodology for low power and arametric robustness through output-quality modulation: Application to color-interpolation filtering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1127-1137. DOI: 10.1109/Tcad.2009.2022197  0.401
2009 Kim JS, Deng L, Mangalagiri P, Irick K, Sobti K, Kandemir M, Narayanan V, Chakrabarti C, Pitsianis N, Sun X. An automated framework for accelerating numerical algorithms on reconfigurable platforms using algorithmic/architectural optimization Ieee Transactions On Computers. 58: 1654-1667. DOI: 10.1109/Tc.2009.78  0.413
2009 Seo S, Woh M, Mahlke S, Mudge T, Vijay S, Chakrabarti C. Customizing wide-SIMD architectures for H.264 Proceedings - 2009 International Conference On Embedded Computer Systems: Architectures, Modeling and Simulation, Ic-Samos 2009. 172-179. DOI: 10.1109/ICSAMOS.2009.5289229  0.356
2009 Narvekar ND, Konnanath B, Mehta S, Chintalapati S, AlKamal I, Chakrabarti C, Karam LJ. An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities Proceedings - International Conference On Image Processing, Icip. 2661-2664. DOI: 10.1109/ICIP.2009.5414130  0.34
2009 Papirla V, Chakrabarti C. Energy-aware error control coding for flash memories Proceedings - Design Automation Conference. 658-663.  0.368
2008 Kim Y, Cho Y, Chang N, Chakrabarti C, Cho NI. Extending the lifetime of media recorders constrained by battery and flash memory size Proceedings of the International Symposium On Low Power Electronics and Design. 159-164. DOI: 10.1145/1393921.1393964  0.322
2008 Zhuo J, Chakrabarti C. Energy-efficient dynamic task scheduling algorithms for DVS systems Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1331331.1331341  0.426
2008 Lee K, Chang N, Zhuo J, Chakrabarti C, Kadri S, Vrudhula S. A fuel-cell-battery hybrid for portable embedded systems Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1297666.1297685  0.355
2008 Woh M, Lin Y, Seo S, Mahlke S, Mudge T, Chakrabarti C, Bruce R, Kershaw D, Reid A, Wilder M, Flautner K. From SODA to scotch: The evolution of a wireless baseband processor Proceedings of the Annual International Symposium On Microarchitecture, Micro. 152-163. DOI: 10.1109/MICRO.2008.4771787  0.324
2007 Li Y, Bakkaloglu B, Chakrabarti C. A system level energy model and energy-quality evaluation for integrated transceiver front-ends Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 90-102. DOI: 10.1109/Tvlsi.2007.891095  0.365
2007 Seo S, Mudge T, Zhu Y, Chakrabarti C. Design and analysis of LDPC decoders for software defined radio Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 210-215. DOI: 10.1109/SIPS.2007.4387546  0.337
2007 Qi Q, Chakrabarti C. Sphere decoding for multiprocessor architectures Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 50-55. DOI: 10.1109/SIPS.2007.4387516  0.512
2007 Lin Y, Lee H, Woh M, Harel Y, Mahlke S, Mudge T, Chakrabarti C, Flautner K. SODA: A high-performance DSP architecture for software-defined radio Ieee Micro. 27: 114-123. DOI: 10.1109/Mm.2007.22  0.369
2007 Zhu Y, Chakrabarti C. Memory efficient LDPC code design for high throughput software defined radio (SDR) systems Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2: II9-II12. DOI: 10.1109/ICASSP.2007.366159  0.307
2006 Zhu Y, Li L, Chakrabarti C. Study of energy and performance of space - Time decoding systems in concatenation with turbo decoding Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 86-90. DOI: 10.1109/Tvlsi.2005.863185  0.594
2006 Lin Y, Mahlke S, Mudge T, Chakrabarti C, Reid A, Flautner K. Design and implementation of turbo decoders for software defined radio 2006 Ieee Workshop On Signal Processing Systems Design and Implementation, Sips. 22-27. DOI: 10.1109/SIPS.2006.352549  0.326
2006 Acharya T, Chakrabarti C. A survey on lifting-based discrete wavelet transform architectures Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 42: 321-339. DOI: 10.1007/s11266-006-4191-3  0.319
2005 Chowdhury P, Chakrabarti C. Erratum: Static task-scheduling algorithms for battery-powered DVS systems (IIEE Transactions on Very Large Scale Integration (VLSI) (Feb. 2005.) 13: 2 (226-237)) Ieee Transactions On Very Large Scale Integration Systems. 13. DOI: 10.1109/Tvlsi.2005.846470  0.351
2005 Tiwari M, Zhu Y, Chakrabarti C. Memory sub-banking scheme for high throughput MAP-based SISO decoders Ieee Transactions On Very Large Scale Integration Systems. 13: 494-498. DOI: 10.1109/Tvlsi.2004.842937  0.605
2005 Chowdhury P, Chakrabarti C. Static task-scheduling algorithms for battery-powered DVS systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 226-237. DOI: 10.1109/Tvlsi.2004.840771  0.394
2005 Rahman H, Chakrabarti C. An efficient control point insertion technique for leakage reduction of scaled CMOS circuits Ieee Transactions On Circuits and Systems Ii: Express Briefs. 52: 496-500. DOI: 10.1109/Tcsii.2005.849026  0.329
2005 Qi Q, Chakrabarti C. Improving the battery performance of ad-hoc routing protocols Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2005: 720-725. DOI: 10.1109/SIPS.2005.1579959  0.369
2005 Shiue WT, Chakrabarti C. Multi-module multi-port memory design for low power embedded systems Design Automation For Embedded Systems. 9: 235-261. DOI: 10.1007/S10617-005-1195-3  0.716
2004 Kaza J, Chakrabarti C. Design and implementation of low-energy turbo decoders Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 968-977. DOI: 10.1109/Tvlsi.2004.832942  0.477
2004 Henning R, Chakrabarti C. An approach for adaptively approximating the viterbi algorithm to reduce power consumption while decoding convolutional codes Ieee Transactions On Signal Processing. 52: 1443-1451. DOI: 10.1109/Tsp.2004.826163  0.463
2004 Austin T, Blaauw D, Mahlke S, Mudge T, Chakrabarti C, Wolf W. Mobile supercomputers Computer. 37: 81-83. DOI: 10.1109/Mc.2004.1297253  0.362
2004 Manzak A, Chakrabarti C. Optimum buffer size for dynamic voltage processors Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3254: 711-721.  0.73
2003 Manzak A, Chakrabarti C. Variable voltage task scheduling algorithms for minimizing energy/power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 270-276. DOI: 10.1109/Tvlsi.2003.810801  0.773
2002 Andra K, Chakrabarti C, Acharya T. A high performance JPEG2000 architecture Proceedings - Ieee International Symposium On Circuits and Systems. 1. DOI: 10.1109/Tcsvt.2003.809834  0.763
2002 Henning R, Chakrabarti C. An approach to switching activity consideration during high-level, low-power design space exploration Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 49: 339-351. DOI: 10.1109/Tcsii.2002.801209  0.37
2002 Manzak A, Chakrabarti C. A low power scheduling scheme with resources operating at multiple voltages Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 6-14. DOI: 10.1109/92.988725  0.771
2002 Andra K, Chakrabarti C, Acharya T. A VLSI architecture for lifting-based forward and inverse wavelet transform Ieee Transactions On Signal Processing. 50: 966-977. DOI: 10.1109/78.992147  0.757
2002 Kaza J, Chakrabarti C. Energy-efficient turbo decoder Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 3.  0.336
2002 Henning R, Chakrabarti C. Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 68-71.  0.352
2001 Andra K, Acharya T, Chakrabarti C. Efficient VLSI implementation of bit plane coder of JPEG2000 Proceedings of Spie - the International Society For Optical Engineering. 4472: 246-257. DOI: 10.1117/12.449757  0.364
2001 Shiue WT, Chakrabarti C. Memory Design and Exploration for Low Power, Embedded Systems Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 29: 167-178. DOI: 10.1023/A:1012227328646  0.689
2001 Manzak A, Chakrabarti C. Voltage scaling for energy minimization with QoS constraints Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 438-443.  0.753
2001 Manzak A, Chakrabarti C. Variable voltage task scheduling algorithms for minimizing energy Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 279-282.  0.748
2000 Shiue WT, Chakrabarti C. Low-power scheduling with resources operating at multiple voltages Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 47: 536-543. DOI: 10.1109/82.847069  0.686
2000 Chakrabarti C, Lucke LE. VLSI architectures for Weighted Order Statistic (WOS) filters Signal Processing. 80: 1419-1433. DOI: 10.1016/S0165-1684(00)00046-3  0.313
2000 Manzak A, Chakrabarti C. Variable voltage task scheduling for minimizing energy or minimizing power Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 6: 3239-3242.  0.749
2000 Andra K, Acharya T, Chakrabarti C. A multi-bit binary arithmetic coding technique Ieee International Conference On Image Processing. 1: 928-931.  0.378
1999 Chakrabarti C, Mumford C. Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 289-298. DOI: 10.1109/92.784090  0.479
1999 Srivatsan K, Chakrabarti C, Lucke LE. A new register allocation scheme for low-power data format converters Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 46: 1250-1253. DOI: 10.1109/82.793717  0.386
1998 Li H, Chakrabarti C. Hardware design of a 2-D motion estimation system based on the Hough transform Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 45: 80-95. DOI: 10.1109/82.659459  0.336
1996 Li HL, Chakrabarti C. A new architecture for the viterbi decoder for code rate k/n Ieee Transactions On Communications. 44: 158-164. DOI: 10.1109/26.486608  0.316
1995 Lucke L, Chakrabarti C. A digit-serial architecture for gray-scale morphological filtering. Ieee Transactions On Image Processing : a Publication of the Ieee Signal Processing Society. 4: 387-91. PMID 18289989 DOI: 10.1109/83.366486  0.353
1995 Li Hl, Chakrabarti C. A New Architecture for the Viterbi Decoder for Code Rate k/n1 Ieee Transactions On Communications. 43: 3101-3101. DOI: 10.1109/TCOMM.1995.477516  0.301
1995 Chakrabarti C, Vishwanath M. Efficient Realizations of the Discrete and Continuous Wavelet Transforms: From Single Chip Implementations to Mappings on SIMD Array Computers Ieee Transactions On Signal Processing. 43: 759-771. DOI: 10.1109/78.370630  0.451
1995 Gupta G, Chakrabarti C. Architectures for Hierarchical and Other Block Matching Algorithms Ieee Transactions On Circuits and Systems For Video Technology. 5: 477-489. DOI: 10.1109/76.475890  0.484
1994 Chakrabarti C, Wang LY. Novel Sorting Network-Based Architectures for Rank Order Filters Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2: 502-507. DOI: 10.1109/92.335027  0.382
1994 Chakrabarti C. A Comment on ‘On Prime Factor Mapping for the Discrete Hartley Transform’ Ieee Transactions On Signal Processing. 42: 1551-1552. DOI: 10.1109/78.286973  0.335
1994 Chakrabarti C. High Sample Rate Array Architectures for Median Filters Ieee Transactions On Signal Processing. 42: 707-712. DOI: 10.1109/78.277872  0.318
1993 Chakrabarti C. Transactions Briefs Sorting Network Based Architectures for Median Filters Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 40: 723-727. DOI: 10.1109/82.251840  0.357
1993 Chakrabarti C, Raghuramireddy D, Unbehauen R. Comments on "Highly modular systolic structures for denominator-separable 2-D recursive filters" [with reply] Ieee Transactions On Signal Processing. 41: 1734-1736. DOI: 10.1109/78.212759  0.333
1991 Chakrabarti C, JáJá J. VLSI Architectures for Multidimensional Transforms Ieee Transactions On Computers. 40: 1053-1057. DOI: 10.1109/12.83648  0.599
1990 Chakrabarti C, JáJá J. Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition Ieee Transactions On Computers. 39: 1359-1368. DOI: 10.1109/12.61045  0.644
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