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Chih-Kong K. Yang - Publications

Affiliations: 
Electrical Engineering 0303 University of California, Los Angeles, Los Angeles, CA 
Area:
Electronics and Electrical Engineering, Computer Engineering
Website:
https://www.ee.ucla.edu/chih-kong-ken-yang/
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11 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Ismail Y, Lee H, Pamarti S, Yang CK. A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology Ieee Journal of Solid-State Circuits. 52: 781-798. DOI: 10.1109/Jssc.2016.2636876  0.345
2013 Ren F, Park H, Yang CK, Markovic D. Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs Ieee Transactions On Circuits and Systems I: Regular Papers. 60: 2932-2939. DOI: 10.1109/Tcsi.2013.2252653  0.526
2013 Chen M, Hafez AA, Yang CK. A 0.1–1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection Ieee Journal of Solid-State Circuits. 48: 2681-2692. DOI: 10.1109/Jssc.2013.2274892  0.345
2013 Ali T, Drost R, Ho R, Yang CK. A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding Ieee Journal of Solid-State Circuits. 48: 1085-1098. DOI: 10.1109/Jssc.2013.2239013  0.343
2012 Dorrance R, Ren F, Toriyama Y, Hafez AA, Yang CK, Markovic D. Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell for STT-RAMs Ieee Transactions On Electron Devices. 59: 878-887. DOI: 10.1109/Ted.2011.2182053  0.335
2012 Chen E, Yousry R, Yang CK. Power Optimized ADC-Based Serial Link Receiver Ieee Journal of Solid-State Circuits. 47: 938-951. DOI: 10.1109/Jssc.2012.2185356  0.523
2010 Stojanovic VM, Yang CK, Ho R. Guest Editorial for Special Issue on High-Performance Multichip Interconnections Ieee Transactions On Circuits and Systems Ii-Express Briefs. 57: 317-318. DOI: 10.1109/Tcsii.2010.2048057  0.531
2008 Seckin U, Yang CK. A Comprehensive Delay Model for CMOS CML Circuits Ieee Transactions On Circuits and Systems. 55: 2608-2618. DOI: 10.1109/Tcsi.2008.920069  0.357
2007 Lee J, Hatcher G, Vandenberghe L, Yang CK. Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies Ieee Transactions On Very Large Scale Integration Systems. 15: 1017-1027. DOI: 10.1109/Tvlsi.2007.902204  0.354
1998 Horowitz M, Yang CK, Sidiropoulos S. High-speed electrical signaling: overview and limitations Ieee Micro. 18: 12-24. DOI: 10.1109/40.653013  0.524
1996 Yang CK, Horowitz MA. A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links Ieee Journal of Solid-State Circuits. 31: 2015-2023. DOI: 10.1109/4.545825  0.339
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