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Kwang-Hoon Oh, Ph.D. - Publications

Affiliations: 
2003 Stanford University, Palo Alto, CA 
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9 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2007 Ji I, Cho K, Choi Y, Kim S, Oh K, Yun C, Han M. A New Insulated Gate Bipolar Transistor Structure employing an Embedded Over-current Protection Device The Japan Society of Applied Physics. 2007: 740-741. DOI: 10.7567/Ssdm.2007.B-6-4  0.451
2007 Ji I, Choi Y, Jeon B, Lee S, Oh K, Yun C, Han Y, Lee B, Han M. A New 1200 V Punch Through-Insulated Gate Bipolar Transistor with Protection Circuit Employing Lateral Insulated Gate Bipolar Transistor and Floating p-Well Voltage Sensing Scheme Japanese Journal of Applied Physics. 46: 2037-2040. DOI: 10.1143/Jjap.46.2037  0.472
2007 Oh K, Lee SC, Kim E, Lee JH, Lee K, Kim S, Yun C. Experimental Investigation of Pulsed-Laser-Annealed Ultralow-Conduction-Loss 600-V Nonpunchthrough Insulated-Gate Bipolar Transistors Ieee Transactions On Electron Devices. 54: 3103-3106. DOI: 10.1109/Ted.2007.906971  0.325
2006 Ji I, Choi Y, Jeon B, Lee S, Kim S, Oh K, Yun C, Han M. A New 1200V PT-IGBT with Protection Circuit employing the Lateral IGBT and Floating p-well Voltage Sensing Scheme The Japan Society of Applied Physics. 2006: 512-513. DOI: 10.7567/Ssdm.2006.P-3-7  0.378
2006 Oh K, Lee J, Lee K, Kim YC, Yun C. A simulation study on novel field stop IGBTs using superjunction Ieee Transactions On Electron Devices. 53: 884-890. DOI: 10.1109/Ted.2006.870278  0.447
2006 Oh K, Kim YC, Lee KH, Yun CM. Investigation of short-circuit failure limited by dynamic-avalanche capability in 600-V punchthrough IGBTs Ieee Transactions On Device and Materials Reliability. 6: 2-8. DOI: 10.1109/Tdmr.2006.870338  0.415
2002 Oh K, Duvvury C, Banerjee K, Dutton RW. Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors Ieee Transactions On Electron Devices. 49: 2171-2182. DOI: 10.1109/Ted.2002.805049  0.472
2002 Oh K, Duvvury C, Banerjee K, Dutton RW. Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors Ieee Transactions On Electron Devices. 49: 2183-2192. DOI: 10.1109/Ted.2002.803627  0.414
2002 Oh K, Duvvury C, Banerjee K, Dutton RW. Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs Ieee Transactions On Device and Materials Reliability. 2: 36-42. DOI: 10.1109/Tdmr.2002.802113  0.451
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