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Meng-Hsueh Chiang, Ph.D. - Publications

Affiliations: 
2001 University of Florida, Gainesville, Gainesville, FL, United States 
Area:
Electronics and Electrical Engineering
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22 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Wu Y, Ding F, Connelly D, Chiang M, Chen JF, Liu TK. Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by Inserted-Oxide FinFET Technology Ieee Transactions On Electron Devices. 66: 1754-1759. DOI: 10.1109/Ted.2019.2900921  0.448
2018 Hsieh Y, Chen S, Chen N, Lee W, Tsai J, Chen C, Chiang M, Lu DD, Kao K. An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications Ieee Transactions On Electron Devices. 65: 855-859. DOI: 10.1109/Ted.2018.2791467  0.357
2017 Wu Y, Ding F, Connelly D, Zheng P, Chiang M, Chen JF, Liu TK. Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology Ieee Transactions On Electron Devices. 64: 4193-4199. DOI: 10.1109/Ted.2017.2736442  0.393
2017 Liu H, Lin C, Hsu W, Lee C, Chiang M, Sun W, Wei S, Yu S. Integration of Gate Recessing and In Situ Cl − Doped Al 2 O 3 for Enhancement-Mode AlGaN/GaN MOSHEMTs Fabrication Ieee Electron Device Letters. 38: 91-94. DOI: 10.1109/Led.2016.2625304  0.373
2017 Huang Y, Chiang M, Wang S, Fossum JG. GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node Ieee Journal of the Electron Devices Society. 5: 164-169. DOI: 10.1109/Jeds.2017.2689738  0.625
2016 Chen CY, Lin JT, Chiang MH. Subthreshold Kink Effect Revisited and Optimized for Si Nanowire MOSFETs Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2512660  0.485
2015 Chiang MH, Hsu KH, Ding WW, Yang BR. A Predictive Compact Model of Bipolar RRAM Cells for Circuit Simulations Ieee Transactions On Electron Devices. 62: 2176-2183. DOI: 10.1109/Ted.2015.2428293  0.34
2014 Liu HY, Hsu W, Lee CS, Chou BY, Liao YB, Chiang M. Investigation of temperature-dependent characteristics of AlGaN/GaN MOS-HEMT by using hydrogen peroxide oxidation technique Ieee Transactions On Electron Devices. 61: 2760-2766. DOI: 10.1109/Ted.2014.2327123  0.386
2014 Liao Y, Chiang M, Damrongplasit N, Hsu W, Liu TK. Design of Gate-All-Around Silicon MOSFETs for 6-T SRAM Area Efficiency and Yield Ieee Transactions On Electron Devices. 61: 2371-2377. DOI: 10.1109/Ted.2014.2323059  0.462
2014 Liao Y, Chiang M, Lai Y, Hsu W. Stack Gate Technique for Dopingless Bulk FinFETs Ieee Transactions On Electron Devices. 61: 963-968. DOI: 10.1109/Ted.2014.2306012  0.427
2014 Chou BY, Lee CS, Yang CL, Hsu W, Liu HY, Chiang M, Sun WC, Wei SY, Yu SM. TiO2-dielectric AlGaN/GaN/Si metal-oxide-semiconductor high electron mobility transistors by using nonvacuum ultrasonic spray pyrolysis deposition Ieee Electron Device Letters. 35: 1091-1093. DOI: 10.1109/Led.2014.2354643  0.432
2012 Chu KY, Cheng SY, Chiang MH, Liu YJ, Huang CC, Chen TY, Hsu CS, Liu WC, Cheng WY, Lin BC. Comprehensive study of InGaP/InGaAs/GaAs dual channel pseudomorphic high electron mobility transistors Solid-State Electronics. 72: 22-28. DOI: 10.1016/J.Sse.2011.09.009  0.437
2012 Liao Y, Chiang M, Kim K, Hsu W. Assessment of structure variation in silicon nanowire FETs and impact on SRAM Microelectronics Journal. 43: 300-304. DOI: 10.1016/J.Mejo.2011.12.002  0.64
2008 Chiang M, Lin J, Kim K, Chuang C. Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications Ieee Transactions On Electron Devices. 55: 2423-2428. DOI: 10.1109/Ted.2008.927664  0.491
2007 Chiang M, Lin J, Kim K, Chuang C. Random Dopant Fluctuation in Limited-Width FinFET Technologies Ieee Transactions On Electron Devices. 54: 2055-2060. DOI: 10.1109/Ted.2007.901154  0.44
2006 Chiang M, Kim K, Chuang C, Tretz C. High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices Ieee Transactions On Electron Devices. 53: 2370-2377. DOI: 10.1109/Ted.2006.881052  0.675
2006 Chiang M, Lin CN, Lin GS. Threshold voltage sensitivity to doping density in extremely scaled MOSFETs Semiconductor Science and Technology. 21: 190-193. DOI: 10.1088/0268-1242/21/2/017  0.443
2005 Chiang M, Kim K, Tretz C, Chuang C. Novel high-density low-power logic circuit techniques using DG devices Ieee Transactions On Electron Devices. 52: 2339-2342. DOI: 10.1109/Ted.2005.856191  0.447
2005 Cheng S, Chen C, Chen J, Liu W, Chang W, Chiang M. Comprehensive studies of InGaP/GaAs heterojunction bipolar transistors with different thickness of setback layers Superlattices and Microstructures. 37: 171-183. DOI: 10.1016/J.Spmi.2004.11.003  0.358
2004 Fossum JG, Ge L, Chiang M, Trivedi VP, Chowdhury MM, Mathew L, Workman GO, Nguyen BY. A process/physics-based compact model for nonclassical CMOS device and circuit design Solid-State Electronics. 48: 919-926. DOI: 10.1016/J.Sse.2003.12.030  0.654
2002 Fossum JG, Ge L, Chiang M. Speed superiority of scaled double-gate CMOS Ieee Transactions On Electron Devices. 49: 808-811. DOI: 10.1109/16.998588  0.67
1998 Possum JG, Chiang MH, Houston TW. Design issues and insights for low-voltage high-density SOI DRAM Ieee Transactions On Electron Devices. 45: 1055-1062. DOI: 10.1109/16.669528  0.435
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