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Aditya Bansal, Ph.D. - Publications

Affiliations: 
2007 Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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14 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Dalela D, Gupta P, Dalela D, Bansal A, Govil T, Goel A, Sankhwar SN. Meatal Occlusive Disease in Adult Males: Are There Any Clinical Variations. Urologia Internationalis. PMID 27160440 DOI: 10.1159/000446221  0.317
2014 Warnock J, Chan Y, Harrer H, Carey S, Salem G, Malone D, Puri R, Zitz JA, Jatkowski A, Strevig G, Datta A, Gattiker A, Bansal A, Mayer G, Chan YH, et al. Circuit and physical design of the zenterprise™ ec12 microprocessor chips and multi-chip module Ieee Journal of Solid-State Circuits. 49: 9-18. DOI: 10.1109/Jssc.2013.2284647  0.383
2009 Kim JJ, Bansal A, Rao R, Lo SH, Chuang CT. Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors Ieee Electron Device Letters. 30: 852-854. DOI: 10.1109/Led.2009.2024014  0.59
2009 Bansal A, Rao R, Kim JJ, Zafar S, Stathis JH, Chuang CT. Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability Microelectronics Reliability. 49: 642-649. DOI: 10.1016/J.Microrel.2009.03.016  0.589
2008 Li J, Bansal A, Ghosh S, Roy K. An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs Acm Journal On Emerging Technologies in Computing Systems. 4: 13. DOI: 10.1145/1389089.1389093  0.533
2008 Bansal A, Kim J, Kim K, Mukhopadhyay S, Chuang C, Roy K. Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies Ieee Transactions On Electron Devices. 55: 1161-1169. DOI: 10.1109/Ted.2008.918426  0.677
2007 Li J, Bansal A, Roy K. Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for Digital Operation Ieee Transactions On Electron Devices. 54: 2918-2929. DOI: 10.1109/Ted.2007.906940  0.513
2007 Bansal A, Roy K. Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors Ieee Transactions On Electron Devices. 54: 1793-1798. DOI: 10.1109/Ted.2007.898042  0.516
2007 Bansal A, Mukhopadhyay S, Roy K. Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era Ieee Transactions On Electron Devices. 54: 1409-1419. DOI: 10.1109/Ted.2007.895879  0.635
2007 Choi JH, Bansal A, Meterelliyoz M, Murthy J, Roy K. Self-consistent approach to leakage power and temperature estimation to predict thermal runaway in FinFET circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2059-2068. DOI: 10.1109/Tcad.2007.906470  0.648
2006 Paul BC, Bansal A, Roy K. Underlap DGMOS for digital-subthreshold operation Ieee Transactions On Electron Devices. 53: 910-913. DOI: 10.1109/Ted.2006.870271  0.536
2006 Bansal A, Paul BC, Roy K. An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2765-2774. DOI: 10.1109/Tcad.2006.882489  0.443
2005 Bansal A, Roy K. Asymmetric halo CMOSFET to reduce static power dissipation with improved performance Ieee Transactions On Electron Devices. 52: 397-405. DOI: 10.1109/Ted.2005.843969  0.558
2005 Bansal A, Paul BC, Roy K. Modeling and optimization of fringe capacitance of nanoscale DGMOS devices Ieee Transactions On Electron Devices. 52: 256-262. DOI: 10.1109/Ted.2004.842713  0.549
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