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Navin Srivastava, Ph.D. - Publications

Affiliations: 
2009 Electrical & Computer Engineering University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Computer Engineering/ Electronics & Photonics
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8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2012 Xu C, Srivastava N, Suaya R, Banerjee K. Fast high-frequency impedance extraction of horizontal interconnects and inductors in 3-D ICs with multiple substrates Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1698-1710. DOI: 10.1109/Tcad.2012.2203598  0.588
2011 Li H, Srivastava N, Mao JF, Yin WY, Banerjee K. Carbon nanotube vias: Does ballistic electron-phonon transport imply improved performance and reliability? Ieee Transactions On Electron Devices. 58: 2689-2701. DOI: 10.1109/Ted.2011.2157825  0.558
2010 Srivastava N, Xu C, Suaya R, Banerjee K. Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate” [Jul 09 1047-1060 Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 849-849. DOI: 10.1109/Tcad.2010.2047753  0.542
2009 Li H, Xu C, Srivastava N, Banerjee K. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects Ieee Transactions On Electron Devices. 56: 1799-1821. DOI: 10.7567/Ssdm.2009.D-8-1  0.599
2009 Srivastava N, Li H, Kreupl F, Banerjee K. On the applicability of single-walled carbon nanotubes as VLSI interconnects Ieee Transactions On Nanotechnology. 8: 542-559. DOI: 10.1109/Tnano.2009.2013945  0.579
2009 Srivastava N, Suaya R, Banerjee K. Analytical expressions for high-frequency VLSI interconnect impedance extraction in the presence of a multilayer conductive substrate Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1047-1060. DOI: 10.1109/Tcad.2009.2017432  0.554
2007 Mysore S, Agrawal B, Srivastava N, Lin S, Banerjee K, Sherwood T. 3D Integration for Introspection Ieee Micro. 27: 77-83. DOI: 10.1109/Mm.2007.1  0.505
2004 Srivastava N, Banerjee K. Interconnect challenges for nanoscale electronic circuits Jom. 56: 30-31. DOI: 10.1007/S11837-004-0285-1  0.513
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