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Larry Pileggi - Publications

Affiliations: 
Electrical and Computer Engineering Carnegie Mellon University, Pittsburgh, PA 
Area:
Electronics and Electrical Engineering, Computer Engineering
Website:
https://www.ece.cmu.edu/directory/bios/pileggi-larry.html
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88 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Isgenc MM, Martins MGA, Zackriya VM, Pagliarini SN, Pileggi L. Logic IP for Low-Cost IC Design in Advanced CMOS Nodes Ieee Transactions On Very Large Scale Integration Systems. 28: 585-595. DOI: 10.1109/Tvlsi.2019.2942825  0.477
2020 Jereminov M, Bromberg DM, Pandey A, Wagner MR, Pileggi L. Evaluating Feasibility Within Power Flow Ieee Transactions On Smart Grid. 11: 3522-3534. DOI: 10.1109/Tsg.2020.2966930  0.317
2020 Jovicic A, Jereminov M, Pileggi L, Hug G. Enhanced Modelling Framework for Equivalent Circuit-Based Power System State Estimation Ieee Transactions On Power Systems. 35: 3790-3799. DOI: 10.1109/Tpwrs.2020.2974459  0.342
2020 Martins MGA, Pagliarini SN, Isgenc MM, Pileggi L. From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 520-532. DOI: 10.1109/Tcad.2018.2889772  0.406
2019 Pagliarini SN, Bhuin S, Isgenc MM, Biswas AK, Pileggi L. A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks. Ieee Transactions On Neural Networks and Learning Systems. PMID 31226090 DOI: 10.1109/Tnnls.2019.2917819  0.431
2019 Jereminov M, Pandey A, Pileggi L. Equivalent Circuit Formulation for Solving AC Optimal Power Flow Ieee Transactions On Power Systems. 34: 2354-2365. DOI: 10.1109/Tpwrs.2018.2888907  0.37
2019 Pandey A, Jereminov M, Wagner MR, Bromberg DM, Hug G, Pileggi L. Robust Power Flow and Three-Phase Power Flow Analyses Ieee Transactions On Power Systems. 34: 616-626. DOI: 10.1109/Tpwrs.2018.2863042  0.329
2018 Pagliarini SN, Isgenc MM, Martins MGA, Pileggi L. Application and Product-Volume-Specific Customization of BEOL Metal Pitch Ieee Transactions On Very Large Scale Integration Systems. 26: 1627-1636. DOI: 10.1109/Tvlsi.2018.2828387  0.421
2018 Liu S, Rabuske T, Paramesh J, Pileggi L, Fernandes J. Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 458-470. DOI: 10.1109/Tcsi.2017.2723799  0.365
2016 Darwish M, Calayir V, Pileggi L, Weldon JA. Ultracompact Graphene Multigate Variable Resistor for Neuromorphic Computing Ieee Transactions On Nanotechnology. 15: 318-327. DOI: 10.1109/Tnano.2016.2525039  0.786
2016 Pandey A, Jereminov M, Li X, Hug G, Pileggi L. Aggregated load and generation equivalent circuit models with semi-empirical data fitting Arxiv: Systems and Control. 7790066. DOI: 10.1109/Igesc.2016.7790066  0.334
2016 Jackson TC, Shi R, Sharma AA, Bain JA, Weldon JA, Pileggi L. Implementing delay insensitive oscillatory neural networks using CMOS and emerging technology Analog Integrated Circuits and Signal Processing. 1-11. DOI: 10.1007/S10470-016-0803-4  0.406
2015 Vaidyanathan K, Zhu Q, Liebmann L, Lai K, Wu S, Liu R, Liu Y, Strojwas A, Pileggi L. Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip Journal of Micro/ Nanolithography, Mems, and Moems. 14. DOI: 10.1117/1.Jmm.14.1.011007  0.704
2015 Liu R, Pileggi L. Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 651-655. DOI: 10.1109/Tcsii.2015.2404222  0.381
2015 Sabry Aly MM, Gao M, Hills G, Lee C, Pitner G, Shulaker MM, Wu TF, Asheghi M, Bokor J, Franchetti F, Goodson KE, Kozyrakis C, Markov I, Olukotun K, Pileggi L, et al. Energy-Efficient Abundant-Data Computing: The N3XT 1,000x Computer. 48: 24-33. DOI: 10.1109/Mc.2015.376  0.349
2015 Jackson TC, Sharma AA, Bain JA, Weldon JA, Pileggi L. Oscillatory neural networks based on TMO nano-oscillators and multi-level RRAM cells Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 230-241. DOI: 10.1109/Jetcas.2015.2433551  0.417
2015 Calayir V, Pileggi L. Device Requirements and Technology-Driven Architecture Optimization for Analog Neurocomputing Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2015.2426497  0.804
2015 Vaidyanathan K, Liebmann L, Strojwas A, Pileggi L. Sub-20 nm design technology co-optimization for standard cell logic Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2015: 124-131. DOI: 10.1109/ICCAD.2014.7001342  0.365
2015 Aly MMS, Gao M, Hills G, Lee CS, Pitner G, Shulaker MM, Wu TF, Asheghi M, Bokor J, Franchetti F, Goodson KE, Kozyrakis C, Markov I, Olukotun K, Pileggi L, et al. Energy-efficient abundant-data computing: The N3XT 1,000 Computer. 48: 24-33. DOI: 10.1063/1.4913279  0.452
2015 Liu R, Pileggi L, Weldon JA. A wideband RF receiver with extended statistical element selection based harmonic rejection calibration Integration, the Vlsi Journal. DOI: 10.1016/J.Vlsi.2015.06.001  0.365
2015 Calayir V, Darwish M, Weldon J, Pileggi L. Analog neuromorphic computing enabled by multi-gate programmable resistive devices Proceedings -Design, Automation and Test in Europe, Date. 2015: 928-931.  0.797
2014 Vaidyanathan K, Liu R, Liebmann L, Lai K, Strojwas AJ, Pileggi L. Design implications of extremely restricted patterning Journal of Micro/ Nanolithography, Mems, and Moems. 13. DOI: 10.1117/1.Jmm.13.3.031309  0.51
2014 Vaidyanathan K, Liu R, Sumbul E, Zhu Q, Franchetti F, Pileggi L. Efficient and secure intellectual property (IP) design with split fabrication Proceedings of the 2014 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2014. 13-18. DOI: 10.1109/HST.2014.6855561  0.301
2014 Vaidyanathan K, Das BP, Sumbul E, Liu R, Pileggi L. Building trusted ICs using split fabrication Proceedings of the 2014 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2014. 1-6. DOI: 10.1109/HST.2014.6855559  0.375
2013 Althoff M, Rajhans A, Krogh BH, Yaldiz S, Li X, Pileggi L. Formal verification of phase-locked loops using reachability analysis and continuization Communications of the Acm. 56: 97-104. DOI: 10.1145/2507771.2507783  0.69
2013 Vaidyanathan K, Liu R, Liebmann L, Lai K, Strojwas A, Pileggi L. Rethinking ASIC design with next generation lithography and process integration Proceedings of Spie - the International Society For Optical Engineering. 8684. DOI: 10.1117/12.2014374  0.479
2013 Plouchart JO, Ferriss MA, Natarajan AS, Valdes-Garcia A, Sadhu B, Rylyakov A, Parker BD, Beakes M, Babakhani A, Yaldiz S, Pileggi L, Harjani R, Reynolds S, Tierno JA, Friedman D. A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS Ieee Transactions On Circuits and Systems I: Regular Papers. 60: 2009-2017. DOI: 10.1109/Tcsi.2013.2265961  0.661
2013 Calayir V, Pileggi L. All-magnetic analog associative memory 2013 Ieee 11th International New Circuits and Systems Conference, Newcas 2013. DOI: 10.1109/NEWCAS.2013.6573563  0.798
2013 Sadhu B, Ferriss MA, Natarajan AS, Yaldiz S, Plouchart J, Rylyakov AV, Valdes-Garcia A, Parker BD, Babakhani A, Reynolds S, Li X, Pileggi L, Harjani R, Tierno JA, Friedman D. Correction to “A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing” Ieee Journal of Solid-State Circuits. 48: 1539-1539. DOI: 10.1109/Jssc.2013.2263875  0.646
2013 Sadhu B, Ferriss MA, Natarajan AS, Yaldiz S, Plouchart JO, Rylyakov AV, Valdes-Garcia A, Parker BD, Babakhani A, Reynolds S, Li X, Pileggi L, Harjani R, Tierno JA, Friedman D. A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing Ieee Journal of Solid-State Circuits. 48: 1138-1150. DOI: 10.1109/Jssc.2013.2252513  0.707
2013 Calayir V, Jackson T, Tazzoli A, Piazza G, Pileggi L. Neurocomputing and associative memories based on ovenized aluminum nitride resonators Proceedings of the International Joint Conference On Neural Networks. DOI: 10.1109/IJCNN.2013.6707002  0.8
2013 Calayir V, Pileggi L. Fully-digital oscillatory associative memories enabled by non-volatile logic Proceedings of the International Joint Conference On Neural Networks. DOI: 10.1109/IJCNN.2013.6706925  0.797
2013 Chen VHC, Keskin G, Pileggi LT. Self-healing circuits using statistical element selection Lecture Notes in Electrical Engineering. 233: 53-75. DOI: 10.1007/978-3-642-36329-0-3  0.382
2012 Morris D, Bromberg D, Zhu JG, Pileggi L. MLogic: Ultra-low voltage non-volatile logic circuits using STT-MTJ devices Proceedings - Design Automation Conference. 486-491. DOI: 10.1145/2228360.2228446  0.321
2012 Morris DH, Bromberg DM, Zhu JG, Pileggi L. Spintronic devices and circuits for low-voltage logic International Journal of High Speed Electronics and Systems. 21. DOI: 10.1142/S012915641250005X  0.423
2012 Huang W, Morris D, Lafferty N, Liebmann L, Vaidyanathan K, Lai K, Pileggi L, Strojwas AJ. Local loops for robust inter-layer routing at sub-20 nm nodes Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.916290  0.426
2012 Vaidyanathan K, Ng SH, Morris D, Lafferty N, Liebmann L, Bender M, Huang W, Lai K, Pileggi L, Strojwas A. Design and manufacturability tradeoffs in unidirectional & bidirectional standard cell layouts in 14 nm node Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.916104  0.442
2012 Bromberg DM, Morris DH, Pileggi L, Zhu JG. Novel STT-MTJ device enabling all-metallic logic circuits Ieee Transactions On Magnetics. 48: 3215-3218. DOI: 10.1109/Tmag.2012.2197186  0.421
2011 Rovner VV, Jhaveri T, Morris D, Strojwas A, Pileggi L. Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes Proceedings of Spie - the International Society For Optical Engineering. 7974. DOI: 10.1117/12.879514  0.807
2011 Keskin G, Proesel J, Plouchart JO, Pileggi L. Exploiting combinatorial redundancy for offset calibration in flash ADCs Ieee Journal of Solid-State Circuits. 46: 1904-1918. DOI: 10.1109/Jssc.2011.2157255  0.463
2011 Wen CY, Paramesh J, Pileggi L, Li J, Kim S, Proesel J, Lam C. Post-silicon calibration of analog CMOS using phase-change memory cells European Solid-State Circuits Conference. 423-426. DOI: 10.1109/ESSCIRC.2011.6044997  0.327
2011 Yaldiz S, Calayir V, Li X, Pileggi L, Natarajan AS, Ferriss MA, Tierno J. Indirect phase noise sensing for self-healing voltage controlled oscillators Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055416  0.721
2011 Morris D, Vaidyanathan K, Lafferty N, Lai K, Liebmann L, Pileggi L. Design of embedded memory and logic based on pattern constructs Digest of Technical Papers - Symposium On Vlsi Technology. 104-105.  0.37
2010 Liebmann L, Hibbeler J, Hieter N, Pileggi L, Jhaveri T, Moe M, Rovner V. Demonstrating the benefits of template-based design-technology co-optimization Proceedings of Spie - the International Society For Optical Engineering. 7641. DOI: 10.1117/12.848244  0.811
2010 Jhaveri T, Arslan U, Rovner V, Strojwas A, Pileggi L. Application of the cost-per-good-die metric for process design co-optimization Proceedings of Spie - the International Society For Optical Engineering. 7641. DOI: 10.1117/12.846556  0.787
2010 Morris D, Rovner V, Pileggi L, Strojwas A, Vaidyanathan K. Enabling application-specific integrated circuits on limited pattern constructs Digest of Technical Papers - Symposium On Vlsi Technology. 139-140. DOI: 10.1109/VLSIT.2010.5556202  0.386
2010 Jhaveri T, Rovner V, Liebmann L, Pileggi L, Strojwas AJ, Hibbeler JD. Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 509-527. DOI: 10.1109/Tcad.2010.2042882  0.822
2010 Keskin G, Proesel J, Pileggi L. Statistical modeling and post manufacturing configuration for scaled analog CMOS Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617625  0.372
2009 Jhaveri T, Strojwas A, Pileggi L, Rovner V. Economic assessment of lithography strategies for the 22nm technology node Proceedings of Spie - the International Society For Optical Engineering. 7488. DOI: 10.1117/12.837240  0.313
2009 Liebmann L, Pileggi L, Hibbeler J, Rovner V, Jhaveri T, Northrop G. Simplify to Survive, prescriptive layouts ensure profitable scaling to 32nm and beyond Proceedings of Spie - the International Society For Optical Engineering. 7275. DOI: 10.1117/12.814701  0.816
2009 Jhaveri T, Stobert I, Liebmann L, Karakatsanis P, Rovner V, Strojwas A, Pileggi L. OPC simplification and mask cost reduction using regular design fabrics Proceedings of Spie - the International Society For Optical Engineering. 7274. DOI: 10.1117/12.814406  0.807
2009 Xu Y, Hsiung KL, Li X, Pileggi LT, Boyd SP. Regular analog/RF integrated circuits design using optimization with recourse including ellipsoidal uncertainty Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 623-637. DOI: 10.1109/Tcad.2009.2013996  0.397
2009 Yaldiz S, Arslan U, Li X, Pileggi L. Efficient statistical analysis of read timing failures in sram circuits Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 617-621. DOI: 10.1109/ISQED.2009.4810365  0.714
2009 Wang J, Yaldiz S, Li X, Pileggi LT. SRAM parametric failure analysis Proceedings - Design Automation Conference. 496-501.  0.598
2008 Jhaveri T, Strojwas A, Pileggi L, Rovner V. Enabling technology scaling with "in production" lithography processes Proceedings of Spie - the International Society For Optical Engineering. 6924. DOI: 10.1117/12.776484  0.804
2008 Li X, Le J, Celik M, Pileggi LT. Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1041-1054. DOI: 10.1109/Tcad.2008.923241  0.6
2008 Brown JG, Taylor B, Blanton RD, Pileggi L. Automated testability enhancements for logic brick libraries Proceedings -Design, Automation and Test in Europe, Date. 480-485. DOI: 10.1109/DATE.2008.4484727  0.339
2008 Pileggi L, Keskin G, Li X, Mai K, Proesel J. Mismatch analysis and statistical design at 65 nm and below Proceedings of the Custom Integrated Circuits Conference. 9-12. DOI: 10.1109/CICC.2008.4672006  0.349
2007 Li X, Le J, Gopalakrishnan P, Pileggi LT. Asymptotic probability extraction for nonnormal performance distributions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 16-37. DOI: 10.1109/Tcad.2006.882593  0.587
2007 Li X, Gopalakrishnan P, Xu Y, Pileggi LT. Robust analog/RF circuit design with projection-based performance modeling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2-15. DOI: 10.1109/Tcad.2006.882513  0.363
2007 Li X, Taylor B, Chien Y, Pileggi LT. Adaptive post-silicon tuning for analog circuits: Concept, analysis and optimization Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 450-457. DOI: 10.1109/ICCAD.2007.4397306  0.341
2007 Wang J, Li X, Pileggi LT. Parameterized macromodeling for analog system-level design exploration Proceedings - Design Automation Conference. 940-943. DOI: 10.1109/DAC.2007.375299  0.321
2007 Taylor B, Pileggi L. Exact combinatorial optimization methods for physical design of regular logic bricks Proceedings - Design Automation Conference. 344-349. DOI: 10.1109/DAC.2007.375184  0.331
2006 Jhaveri T, Pileggi L, Rovner V, Strojwas AJ. Maximization of layout printability/manufacturability by extreme layout regularity Proceedings of Spie - the International Society For Optical Engineering. 6156. DOI: 10.1117/1.2781583  0.813
2006 Kim YT, Rovner V, Pileggi LT, Kheterpal V. Design methodology of regular logic bricks for robust integrated circuits Ieee International Conference On Computer Design, Iccd 2006. 162-167. DOI: 10.1109/ICCD.2006.4380810  0.397
2005 Li X, Wang J, Pileggi LT, Chen TS, Chiang W. Performance-centering optimization for system-level analog design exploration Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 421-428. DOI: 10.1109/ICCAD.2005.1560105  0.353
2005 Xu Y, Nausieda I, Hsiung KL, Boyd S, Li X, Pileggi L. OPERA: Optimization with ellipsoidal uncertainty for robust analog IC design Proceedings - Design Automation Conference. 632-637.  0.358
2005 Zhan Y, Strojwas AJ, Li X, Pileggi LT, Newmark D, Sharma M. Correlation-aware statistical timing analysis with non-gaussian delay distributions Proceedings - Design Automation Conference. 77-82.  0.305
2004 Xu Y, Boone C, Pileggi LT. Metal-mask configurable RF front-end circuits Ieee Radio Frequency Integrated Circuits Symposium, Rfic, Digest of Technical Papers. 547-550. DOI: 10.1109/JSSC.2004.831798  0.344
2004 Koorapaty A, Kheterpal V, Gopalakrishnan P, Fu M, Pileggi L. Exploring logic block granularity for regular fabrics Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 468-473. DOI: 10.1109/DATE.2004.1268890  0.369
2004 Xu Y, Pileggi LT, Boyd SP. ORACLE: Optimization with recourse of analog circuits including layout extraction Proceedings - Design Automation Conference. 151-154.  0.386
2004 Kheterpal V, Strojwas AJ, Pileggi L. Routing architecture exploration for regular fabrics Proceedings - Design Automation Conference. 204-207.  0.324
2004 Li X, Gopalakrishnan P, Xu Y, Pileggi LT. Robust analog/RF circuit design with projection-based posynomial modeling Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 855-862.  0.384
2004 Batra R, Li P, Pileggi LT, Chien YT. A methodology for analog circuit macromodeling Bmas 2004 - Proceedings of the 2004 Ieee International Behavioral Modeling and Simulation Conference. 41-46.  0.303
2003 Li P, Pileggi LT. Efficient per-nonlinearity distortion analysis for analog and RF circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1297-1309. DOI: 10.1109/Tcad.2003.818130  0.316
2003 Pandini D, Pileggi LT, Strojwas AJ. Global and local congestion optimization in technology mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 498-506. DOI: 10.1109/Tcad.2003.809646  0.732
2003 Koorapaty A, Pileggi L, Schmit H. Heterogeneous logic block architectures for via-patterned programmable fabrics Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2778: 426-436.  0.366
2003 Pileggi L. Exploring regular fabrics to optimize the performance-cost trade-off Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 47: 694-698.  0.355
2003 Patel C, Cozzie A, Schmit H, Pileggi L. An architectural exploration of via patterned gate arrays Proceedings of the International Symposium On Physical Design. 184-189.  0.329
2003 Pandini D, Pileggi LT, Strojwas AJ. Bounding the efforts on congestion optimization for physical synthesis Proceedings of the Ieee Great Lakes Symposium On Vlsi. 7-10.  0.727
2003 Tong KY, Kheterpal V, Rovner V, Pileggi L, Schmit H, Puri R. Regular logic fabrics for a via patterned gate array (VPGA) Proceedings of the Custom Integrated Circuits Conference. 53-56.  0.385
2002 Lin T, Pileggi LT. Throughput-driven IC communication fabric synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 274-279. DOI: 10.1145/774572.774613  0.323
2002 Pandini D, Pileggi LT, Strojwas AJ. Congestion-aware logic synthesis Proceedings -Design, Automation and Test in Europe, Date. 664-671. DOI: 10.1109/DATE.2002.998370  0.758
2002 Zheng H, Krauter B, Beattie M, Pileggi L. Window-based susceptance models for large-scale RLC circuit analyses Proceedings -Design, Automation and Test in Europe, Date. 628-633. DOI: 10.1109/DATE.2002.998366  0.302
2002 Gopalakrishnan P, Odabasioglu A, Pileggi L, Raje S. An analysis of wire-load model uncertainty problem Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 23-31. DOI: 10.1109/43.974134  0.442
2002 Pandini D, Pileggi LT, Strojwas AJ. Understanding and addressing the impact of wiring congestion during technology mapping Proceedings of the International Symposium On Physical Design. 131-136.  0.722
2001 Gopalakrishnan P, Odabasioglu A, Pileggi L, Raje S. Overcoming wireload model uncertainty during physical design Proceedings of the International Symposium On Physical Design. 182-189.  0.342
1998 Gupta R, Willis J, Pileggi L. Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 457-463. DOI: 10.1109/92.711316  0.359
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