John C. Lach, Ph.D.

Affiliations: 
2000 University of California, Los Angeles, Los Angeles, CA 
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"John Lach"

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William H. Mangione-Smith grad student 2000 UCLA (Computer Science Tree)
 (FPGA physical design partitioning and its applications.)
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Publications

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Anderson MS, Bankole A, Newbold TM, et al. (2019) P4-391: CAREGIVER INPUT IN DESIGN AND USE OF NEW TECHNOLOGIES TO REDUCE AGITATION IN DEMENTIA IN THE HOME SETTING Alzheimer's & Dementia. 15: P1450-P1451
Bankole A, Anderson M, Lach J, et al. (2019) BESI: BEHAVIORAL AND ENVIRONMENTAL SENSING AND INTERVENTION FOR DEMENTIA CAREGIVER EMPOWERMENT The American Journal of Geriatric Psychiatry. 27: S189-S190
Fan D, Lopez Ruiz L, Gong J, et al. (2017) EHDC: An Energy Harvesting Modeling and Profiling Platform for Body Sensor Networks. Ieee Journal of Biomedical and Health Informatics
Chen S, Lach J, Lo B, et al. (2016) Toward Pervasive Gait Analysis With Wearable Sensors: A Systematic Review. Ieee Journal of Biomedical and Health Informatics. 20: 1521-1537
Gong J, Qi Y, Goldman M, et al. (2016) Causality Analysis of Inertial Body Sensors for Multiple Sclerosis Diagnostic Enhancement. Ieee Journal of Biomedical and Health Informatics
Powell HC, Hanson MA, Lach J. (2009) On-body inertial sensing and signal processing for clinical assessment of tremor. Ieee Transactions On Biomedical Circuits and Systems. 3: 108-16
Lu Z, Huang W, Stan MR, et al. (2007) Interconnect lifetime prediction for reliability-aware systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 159-172
Kumar VV, Lach J. (2006) Highly flexible multimode digital signal processing systems using adaptable components and controllers Eurasip Journal On Advances in Signal Processing. 2006: 73-73
Lach J, Mangione-Smith WH, Potkonjak M. (2001) Fingerprinting techniques for field-programmable gate array intellectual property protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1253-1261
Kahng AB, Lach J, Mangione-Smith WH, et al. (2001) Constraint-based watermarking techniques for design IP protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1236-1252
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