Year |
Citation |
Score |
2021 |
Bai Z, Li Q, Chen Q, Niu C, Wei Y, Huang H, Zhao W, Chen N, Yao X, Zhang Q, Mu C, Feng J, Zhu C, Li Z, Ding M, et al. Clinical significance of serum IgM and IgG levels in COVID-19 patients in Hubei Province, China. Journal of Intensive Medicine. 2: 32-38. PMID 36785701 DOI: 10.1016/j.jointm.2021.09.001 |
0.329 |
|
2012 |
Li Z, Zhou Y, Shi W. $O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 437-441. DOI: 10.1109/Tcad.2011.2174639 |
0.624 |
|
2009 |
Hu S, Li Z, Alpert CJ. A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment Ieee Transactions On Circuits and Systems Ii-Express Briefs. 56: 580-584. DOI: 10.1109/Tcsii.2009.2022203 |
0.312 |
|
2008 |
Papa DA, Luo T, Moffitt MD, Sze CN, Li Z, Nam GJ, Alpert CJ, Markov IL. RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2156-2168. DOI: 10.1109/Tcad.2008.2006155 |
0.323 |
|
2007 |
Hu S, Alpert CJ, Hu J, Karandikar SK, Li Z, Shi W, Sze CN. Fast algorithms for slew-constrained minimum cost buffering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2009-2022. DOI: 10.1109/Tcad.2007.906477 |
0.616 |
|
2007 |
Li Z, Zhou Y, Shi W. Wire Sizing for Non-Tree Topology Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 872-880. DOI: 10.1109/Tcad.2006.884572 |
0.55 |
|
2006 |
Li Z, Shi W. An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 484-489. DOI: 10.1109/Tcad.2005.854631 |
0.62 |
|
2005 |
Lu X, Li Z, Qiu W, Walker DMH, Shi W. Longest-path selection for delay test under process variation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1924-1929. DOI: 10.1109/Tcad.2005.852674 |
0.605 |
|
2005 |
Shi W, Li Z. A fast algorithm for optimal buffer insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 879-891. DOI: 10.1109/Tcad.2005.847942 |
0.623 |
|
2003 |
Li Z, Lu X, Qiu W, Shi W, Walker DMH. A circuit level fault model for resistive bridges Acm Transactions On Design Automation of Electronic Systems. 8: 546-559. DOI: 10.1145/944027.944036 |
0.575 |
|
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