James M. Tuck, Ph.D.
Affiliations: | 2007 | University of Illinois, Urbana-Champaign, Urbana-Champaign, IL |
Area:
Computer ScienceGoogle:
"James Tuck"Parents
Sign in to add mentorJosep Torrellas | grad student | 2007 | UIUC | |
(Efficient support for speculative tasking.) |
BETA: Related publications
See more...
Publications
You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect. |
Samara A, Tuck J. (2020) The Case for Domain-Specialized Branch Predictors for Graph-Processing Ieee Computer Architecture Letters. 19: 101-104 |
Alshboul M, Elnawawy H, Elkhouly R, et al. (2019) Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory Acm Transactions On Architecture and Code Optimization. 16: 18 |
Patsilaras G, Tuck J. (2017) ReDirect: Reconfigurable Directories for Multicore Architectures Acm Transactions On Architecture and Code Optimization. 14: 50 |
Wibowo B, Agrawal A, Stanton T, et al. (2016) An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation Acm Transactions On Architecture and Code Optimization. 13: 30 |
Sheikh R, Tuck J, Rotenberg E. (2015) Control-flow decoupling: An approach for timely, non-speculative branching Ieee Transactions On Computers. 64: 2182-2203 |
Koryachko A, Matthiadis A, Ducoste JJ, et al. (2015) Computational approaches to identify regulators of plant stress response using high-throughput gene expression data Current Plant Biology |
Milewicz R, Vanka R, Tuck J, et al. (2015) Lightweight runtime checking of C programs with RTC Computer Languages, Systems and Structures |
Lee S, Tuck J. (2013) Automatic parallelization of fine-grained metafunctions on a chip multiprocessor Acm Transactions On Architecture and Code Optimization. 10: 30 |
Torrellas J, Ceze L, Tuck J, et al. (2009) The Bulk Multicore architecture for improved programmability Communications of the Acm. 52: 58-65 |
Tuck J, Ahn W, Torrellas J, et al. (2009) SoftSig: Software-exposed hardware signatures for code analysis and optimization Ieee Micro. 29: 84-95 |