☰

Dhamin Al-Khalili - Publications

Affiliations: 
Royal Military College of Canada (Canada) 
Area:
Electronics and Electrical Engineering, Computer Science
Tree Info Similar researchers PubMed Report error

55 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Dibaj R, Al-Khalili D, Shams M. Gate Oxide Short Defect Model in FinFETs Journal of Electronic Testing. 34: 351-362. DOI: 10.1007/S10836-018-5727-8  0.464
2017 Gao S, Al-Khalili D, Langlois JMP, Chabini N. Efficient Realization of BCD Multipliers Using FPGAs International Journal of Reconfigurable Computing. 2017: 1-12. DOI: 10.1155/2017/2410408  0.383
2013 Moshgelani F, Al-Khalili D, Rozon C. Ultra-low leakage arithmetic circuits using symmetric and asymmetric finfets Journal of Electrical and Computer Engineering. DOI: 10.1155/2013/454392  0.435
2013 Moshgelani F, Al-Khalili D, Rozon C. Adder circuits using symmetric and asymmetric FinFETs Proceedings - 2013 2nd International Symposium On Instrumentation and Measurement, Sensor Network and Automation, Imsna 2013. 23-26. DOI: 10.1109/IMSNA.2013.6742809  0.372
2012 Gao S, Al-Khalili D, Chabini N. An improved BCD adder using 6-LUT FPGAs 2012 Ieee 10th International New Circuits and Systems Conference, Newcas 2012. 13-16. DOI: 10.1109/NEWCAS.2012.6328944  0.367
2012 Gao S, Al-Khalili D, Chabini N, Langlois P. Asymmetric large size multipliers with optimised FPGA resource utilisation Iet Computers and Digital Techniques. 6: 372-383. DOI: 10.1049/Iet-Cdt.2011.0146  0.45
2012 Gao S, Al-Khalili D, Chabini N. FPGA realization of high performance large size computational functions: Multipliers and applications Analog Integrated Circuits and Signal Processing. 70: 165-179. DOI: 10.1007/S10470-011-9734-2  0.384
2011 El-Masry H, Al-Khalili D. Cell stack length using an enhanced logical effort model for a library-free paradigm 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 703-706. DOI: 10.1109/ICECS.2011.6122371  0.301
2011 Athow JL, Rozon C, Al-Khalili D, Langlois JMP. A CNFET-based characterization framework for digital circuits 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 681-684. DOI: 10.1109/ICECS.2011.6122366  0.322
2011 Gao S, Al-Khalili D, Chabini N. Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 137-140. DOI: 10.1109/ICECS.2011.6122233  0.323
2009 Gao S, Al-Khalili D, Chabini N. Efficient scheme for implementing large size signed multipliers using multigranular embedded DSP blocks in FPGAs International Journal of Reconfigurable Computing. 2009: 1-11. DOI: 10.1155/2009/145130  0.397
2009 Cayouette S, Al-Khalili D. Static power dissipation in adder circuits: The UDSM domain Proceedings of Spie - the International Society For Optical Engineering. 7363. DOI: 10.1117/12.819798  0.316
2009 Gao S, Al-Khalili D, Chabini N. Implementation of large size multipliers using ternary adders and higher order compressors Proceedings of the International Conference On Microelectronics, Icm. 118-121. DOI: 10.1109/ICM.2009.5418675  0.337
2008 El-Masry H, Al-Khalili D. A complementary logic partitioning algorithm for a library-free logic synthesis paradigm Proceedings of Spie - the International Society For Optical Engineering. 6798. DOI: 10.1117/12.759536  0.353
2008 Al-Hertani H, Al-Khalili D, Rozon C. A new total static leakage estimation model for UDSM-based transistor stacks Proceedings of Spie - the International Society For Optical Engineering. 6798. DOI: 10.1117/12.758952  0.328
2008 Gao S, Chabini N, Al-Khalili D. 256×256-bit multiplier using multi-granular embedded DSP blocks in FPGAs 2008 Joint Ieee North-East Workshop On Circuits and Systems and Taisa Conference, Newcas-Taisa. 253-256. DOI: 10.1109/NEWCAS.2008.4606369  0.327
2008 Kong MY, Pierre Langlois JM, Al-Khalili D. Efficient FPGA implementation of complex multipliers using the logarithmic number system Proceedings - Ieee International Symposium On Circuits and Systems. 3154-3157. DOI: 10.1109/ISCAS.2008.4542127  0.316
2008 Al-Hertani H, Al-Khalili D, Rozon C. Gate level static power estimation in UDSM processes Proceedings of the International Conference On Microelectronics, Icm. 212-215. DOI: 10.1109/ICM.2008.5393838  0.304
2008 Gao S, Chabini N, Al-Khalili D. Efficient techniques for realizing large-size signed multipliers in FPGAs Proceedings of the International Conference On Microelectronics, Icm. 1-4. DOI: 10.1109/ICM.2008.5393833  0.313
2008 Al-Hertani H, Al-Khalili D, Rozon C. UDSM subthreshold leakage model for NMOS transistor stacks Microelectronics Journal. 39: 1809-1816. DOI: 10.1016/J.Mejo.2008.05.002  0.393
2008 Gao S, Al-Khalili D, Chabini N. Efficient realization of large size two's complement multipliers using embedded blocks in FPGAs Circuits, Systems, and Signal Processing. 27: 713-731. DOI: 10.1007/S00034-008-9051-X  0.411
2007 Gao S, Chabini N, Al-Khalili D, Langlois JMP. Optimised realisations of large integer multipliers and squarers using embedded block Iet Computers and Digital Techniques. 1: 9-16. DOI: 10.1049/Iet-Cdt:20060074  0.409
2006 Langlois JMP, Al-Khalili D. Carry-free approximate squaring functions with O(n) complexity and O(1) delay Ieee Transactions On Circuits and Systems Ii: Express Briefs. 53: 374-378. DOI: 10.1109/TCSII.2006.873364  0.306
2006 Gao S, Chabini N, Al-Khalili D, Langlois P. Efficient realization of large integer multipliers and squarers 4th International Ieee North-East Workshop On Circuits and Systems, Newcas 2006 - Conference Proceedings. 237-240. DOI: 10.1109/NEWCAS.2006.250896  0.328
2006 Shaw D, Al-Khalili D, Rozon C. Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries Integration, the Vlsi Journal. 39: 382-406. DOI: 10.1016/J.Vlsi.2005.08.002  0.618
2006 Gao S, Chabini N, Al-Khalili D, Langlois P. An optimized design approach for squaring large integers using embedded hardwired multipliers Ieee International Conference On Computer Systems and Applications, 2006. 2006: 248-254.  0.319
2005 Xue J, Al-Khalili D, Rozon CN. Technology mapping in library-free logic synthesis Proceedings of Spie - the International Society For Optical Engineering. 5837: 919-928. DOI: 10.1117/12.608154  0.429
2005 Saaied H, Al-Khalili D, Al-Khalili AJ, Nekili M. Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1637-1643. DOI: 10.1109/Tcad.2005.852034  0.337
2005 Kabbani A, Al-Khalili D, Al-Khalili AJ. Delay analysis of CMOS gates using modified logical effort model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 937-947. DOI: 10.1109/Tcad.2005.847892  0.418
2005 Kabbani A, Al-Khalili D, Al-Khalili AJ. Logical path delay distribution and transistor sizing 3rd International Ieee Northeast Workshop On Circuits and Systems Conference, Newcas 2005. 2005: 391-394. DOI: 10.1109/NEWCAS.2005.1496701  0.324
2005 Al-Hertani H, Al-Khalili D, Rozon C. Leakage power dissipation in udsm logic gates Proceedings of the Third Iasted International Conference On Circuits, Signals, and Systems, Css 2005. 132-136.  0.346
2004 Xue J, Al-Khalili D, Rozon CN. A normalized intrinsic delay model of static CMOS complex gates for deep submicron technologies Conference Proceedings - 2nd Annual Ieee Northeast Workshop On Circuits and Systems, Newcas 2004. 17-20.  0.338
2004 Kabbani A, Al-Khalili D, Al-Khalili AJ. Delay macro modeling of CMOS gates using modified logical effort technique Proceedings Icse 2004 - 2004 Ieee International Conference On Semiconductor Electronics. 56-60.  0.349
2004 Langlois JMP, Al-Khalili D, Al-Hertani H. Carry free, bit parallel approximate squarers with linear complexity and constant delay Conference Proceedings - 2nd Annual Ieee Northeast Workshop On Circuits and Systems, Newcas 2004. 385-388.  0.324
2004 Xue J, Al-Khalili D, Rozon CN. Tree-based transistor topology extraction algorithm for library-free logic synthesis Proceedings Icse 2004 - 2004 Ieee International Conference On Semiconductor Electronics. 242-246.  0.35
2003 Shaw DB, Al-Khalili D, Rozon CN. IC bridge fault modeling for IP blocks using neural network-based VHDL saboteurs Ieee Transactions On Computers. 52: 1285-1297. DOI: 10.1109/TC.2003.1234526  0.63
2003 Yip K, Al-Khalili D. Multilevel logic synthesis using hybrid pass logic and CMOS topologies Iee Proceedings: Circuits, Devices and Systems. 150: 445-452. DOI: 10.1049/ip-cds:20030407  0.386
2002 Shaw D, Al-Khalili D, Rozon C. Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models Integration, the Vlsi Journal. 32: 77-97. DOI: 10.1016/S0167-9260(02)00043-3  0.633
2001 Shaw D, Al-Khalili D, Rozon C. Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation Proceedings - Ieee International Symposium On Circuits and Systems. 5: 263-266. DOI: 10.1109ISCAS.2001.922035  0.465
2001 Shaw D, Al-Khalili D, Rozon C. Automated defect to fault translation for ASIC standard cell libraries Ieee Pacific Rim Conference On Communications, Computers, and Signal Processing - Proceedings. 291-294.  0.479
2001 Shaw D, Al-Khalili D, Rozon C. Accurate CMOS bridge fault modeling with neural network-based VHDL saboteurs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 531-536.  0.481
2000 Rozon C, Al-Khalili D, Adham S, Racz D. Comparing defect coverage for current-mode logic and CMOS VLSI cells Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 1: 429-432. DOI: 10.1109/ICECS.2000.911572  0.371
2000 Sun P, Al-Khalili AJ, Al-Khalili D. A CAD tool for first hand CMOS circuit selection Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 1: 165-168. DOI: 10.1109/ICECS.2000.911509  0.364
1999 Gallant M, Al-Khalili D. Synthesis of low-power CMOS circuits using hybrid topologies Integration, the Vlsi Journal. 27: 143-163. DOI: 10.1016/S0167-9260(99)00004-8  0.458
1999 Pillai RVK, Al-Khalili D, Al-Khalili AJ. An IEEE Compliant Floating Point MAF Ieee Transactions On Very Large Scale Integration Systems. 149-160. DOI: 10.1007/978-0-387-35498-9_14  0.373
1998 Coppens J, Al-Khalili D, Rozon C. VHDL modelling and analysis of fault secure systems Proceedings -Design, Automation and Test in Europe, Date. 148-152. DOI: 10.1109/DATE.1998.655849  0.432
1995 Esonu MO, Al-Khalili AJ, Hariri S, Al-Khalili D. Design techniques for fault-tolerant systolic arrays Journal of Vlsi Signal Processing. 11: 151-168. DOI: 10.1007/BF02106828  0.429
1994 Esonu MO, Al-Khalili AJ, Al-Khalili D. Fault-tolerant design methodology for systolic array architectures Iee Proceedings: Computers and Digital Techniques. 141: 17-28. DOI: 10.1049/ip-cdt:19949816  0.405
1994 Kechichian K, Al-Khalili AJ, Al-Khalili D. Optimizing CMOS combinatorial circuits using multiple attribute decision making techniques Canadian Conference On Electrical and Computer Engineering. 2: 549-552.  0.31
1993 Esonu MO, Al-Khalili D, Rozon C. Fault characterization and testability analysis of emitter coupled logic and comparison with CMOS & BiCMOS circuits Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1714-1717. DOI: 10.1155/1994/70696  0.507
1993 Esonu MO, Al-Khalili D, Rozon C. Fault characterization and testability analysis of emitter coupled logic and comparison with CMOS & BiCMOS circuits Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1714-1717.  0.439
1992 Al-Khalili D, Esonu MO. Optimization of high performance BiCMOS buffer circuit for chip area, delay and power dissipation Microelectronics Journal. 23: 387-402. DOI: 10.1016/0026-2692(92)90118-K  0.359
1992 Al-Khalili D, Rozon C, Stewart B. Testability analysis and fault modeling of BiCMOS circuits Journal of Electronic Testing. 3: 207-217. DOI: 10.1007/Bf00134731  0.508
1991 Esonu MO, Al-Khalili AJ, Al-Khalili D. Variations on the theme for designing fault-tolerant systolic array architectures Ieee Pacific Rim Conference On Communications, Computers and Signal Processing Conference Proceedings. 107-110.  0.412
1991 Stewart BE, Al-Khalili D, Rozon C. Defect modelling and testability analysis of BiCMOS circuits Canadian Journal of Electrical and Computer Engineering. 16: 148-152.  0.471
Show low-probability matches.