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Himanshu Kaul, Ph.D. - Publications

Affiliations: 
2005 University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Electronics and Electrical Engineering
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38 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Kumar R, Suresh V, Kar M, Satpathy S, Anders MA, Kaul H, Agarwal A, Hsu S, Chen GK, Krishnamurthy RK, De V, Mathew SK. A 4900-$\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition Ieee Journal of Solid-State Circuits. 55: 945-955. DOI: 10.1109/Jssc.2019.2960482  0.61
2019 Satpathy SK, Mathew SK, Kumar R, Suresh V, Anders MA, Kaul H, Agarwal A, Hsu S, Krishnamurthy RK, De V. An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS Ieee Journal of Solid-State Circuits. 54: 1074-1085. DOI: 10.1109/Jssc.2018.2886350  0.389
2017 Satpathy S, Mathew SK, Suresh V, Anders MA, Kaul H, Agarwal A, Hsu SK, Chen G, Krishnamurthy RK, De VK. A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS Ieee Journal of Solid-State Circuits. 52: 940-949. DOI: 10.1109/Jssc.2016.2636859  0.599
2016 Mathew SK, Johnston D, Satpathy S, Suresh V, Newman P, Anders MA, Kaul H, Agarwal A, Hsu SK, Chen G, Krishnamurthy RK. μrNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS Ieee Journal of Solid-State Circuits. 51: 1695-1704. DOI: 10.1109/Jssc.2016.2558490  0.623
2016 Kaul H, Anders MA, Mathew SK, Chen G, Satpathy SK, Hsu SK, Agarwal A, Krishnamurthy RK. 14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 260-261. DOI: 10.1109/ISSCC.2016.7418006  0.307
2015 Mathew S, Satpathy S, Suresh V, Anders M, Kaul H, Agarwal A, Hsu S, Chen G, Krishnamurthy R. 340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(24)2 Polynomials in 22 nm Tri-Gate CMOS Ieee Journal of Solid-State Circuits. 50: 1048-1058. DOI: 10.1109/Jssc.2014.2384039  0.62
2014 Mathew SK, Satpathy SK, Anders MA, Kaul H, Hsu SK, Agarwal A, Chen GK, Parker RJ, Krishnamurthy RK, De V. 16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 278-279. DOI: 10.1109/ISSCC.2014.6757433  0.548
2013 Hsu SK, Agarwal A, Anders MA, Mathew SK, Kaul H, Sheikh F, Krishnamurthy RK. A 280 mV-to-1.1 v 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm tri-gate CMOS Ieee Journal of Solid-State Circuits. 48: 118-127. DOI: 10.1109/Jssc.2012.2222811  0.377
2012 Mathew SK, Srinivasan S, Anders MA, Kaul H, Hsu SK, Sheikh F, Agarwal A, Satpathy S, Krishnamurthy RK. 2.4 Gbps, 7 mW all-digital PVT-variation tolerant true random number generator for 45 nm CMOS high-performance microprocessors Ieee Journal of Solid-State Circuits. 47: 2807-2821. DOI: 10.1109/Jssc.2012.2217631  0.401
2012 Kaul H, Anders M, Mathew S, Hsu S, Agarwal A, Sheikh F, Krishnamurthy R, Borkar S. A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 182-183. DOI: 10.1109/ISSCC.2012.6176987  0.384
2012 Sheikh F, Mathew S, Anders M, Kaul H, Hsu S, Agarwal A, Krishnamurthy R, Borkar S. A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 184-185. DOI: 10.1109/ISSCC.2012.6176967  0.308
2012 Hsu S, Agarwal A, Anders M, Mathew S, Kaul H, Sheikh F, Krishnamurthy R. A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 178-179. DOI: 10.1109/ISSCC.2012.6176966  0.384
2011 Seo JS, Kaul H, Krishnamurthy R, Sylvester D, Blaauw D. A robust edge encoding technique for energy-efficient multi-cycle interconnect Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 264-273. DOI: 10.1109/Tvlsi.2009.2032422  0.629
2011 Mathew SK, Sheikh F, Kounavis M, Gueron S, Agarwal A, Hsu SK, Kaul H, Anders MA, Krishnamurthy RK. 53 Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45 nm high-performance microprocessors Ieee Journal of Solid-State Circuits. 46: 767-776. DOI: 10.1109/Jssc.2011.2108131  0.36
2011 Agarwal A, Hsu S, Mathew S, Anders M, Kaul H, Sheikh F, Krishnamurthy R. A 128x128b high-speed wide-and match-line content addressable memory in 32nm CMOS European Solid-State Circuits Conference. 83-86. DOI: 10.1109/ESSCIRC.2011.6044920  0.309
2011 Anders MA, Kaul H, Krishnamurthy RK, Borkar SY. Hybrid circuit/packet switched network for energy efficient on-chip interconnections Low Power Networks-On-Chip. 3-20. DOI: 10.1007/978-1-4419-6911-8_1  0.31
2010 Agarwal A, Hsu S, Mathew S, Anders M, Kaul H, Sheikh F, Krishnamurthy R. A 32nm 8.3GHz 64-entry × 32b variation tolerant near-threshold voltage register file Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 105-106. DOI: 10.1109/VLSIC.2010.5560334  0.373
2010 Mathew S, Sheikh F, Agarwal A, Kounavis M, Hsu S, Kaul H, Anders M, Krishnamurthy R. 53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 169-170. DOI: 10.1109/VLSIC.2010.5560310  0.333
2010 Srinivasan S, Mathew S, Ramanarayanan R, Sheikh F, Anders M, Kaul H, Erraguntla V, Krishnamurthy R, Taylor G. 2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 203-204. DOI: 10.1109/VLSIC.2010.5560296  0.358
2010 Kaul H, Anders MA, Mathew SK, Hsu SK, Agarwal A, Krishnamurthy RK, Borkar S. A 300 mV 494GOPS/W reconfigurable dual-supply 4-way SIMD vector processing accelerator in 45 nm CMOS Ieee Journal of Solid-State Circuits. 45: 95-102. DOI: 10.1109/JSSC.2009.2031813  0.347
2010 Anders MA, Kaul H, Hsu SK, Agarwal A, Mathew SK, Sheikh F, Krishnamurthy RK, Borkar S. A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8x8 mesh network-on-chip in 45nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 110-111. DOI: 10.1109/ISSCC.2010.5434078  0.369
2010 Agarwal A, Mathew SK, Hsu SK, Anders MA, Kaul H, Sheikh F, Ramanarayanan R, Srinivasan S, Krishnamurthy R, Borkar S. A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 328-329. DOI: 10.1109/ISSCC.2010.5433903  0.403
2010 Mathew S, Kounavis M, Sheikh F, Hsu S, Agarwal A, Kaul H, Anders M, Berry F, Krishnamurthy R. 3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS Esscirc 2010 - 36th European Solid State Circuits Conference. 198-201. DOI: 10.1109/ESSCIRC.2010.5619895  0.326
2010 Ramanarayanan R, Mathew S, Sheikh F, Srinivasan S, Agarwal A, Hsu S, Kaul H, Anders M, Erraguntla V, Krishnamurthy R. 18Gbps, 50mW reconfigurable multi-mode SHA hashing accelerator in 45nm CMOS Esscirc 2010 - 36th European Solid State Circuits Conference. 210-213. DOI: 10.1109/ESSCIRC.2010.5619892  0.331
2009 Kaul H, Anders MA, Mathew SK, Hsu SK, Agarwal A, Krishnamurthy RK, Borkar S. A 320 mV 56 W 411 GOPS/watt ultra-low voltage motion estimation accelerator in 65 nm CMOS Ieee Journal of Solid-State Circuits. 44: 107-114. DOI: 10.1109/Jssc.2008.2007164  0.37
2008 Kaul H, Anders M, Mathew S, Hsu S, Agarwal A, Krishnamurthy R, Borkar S. A 320mV 56μW 411GOPS/watt ultra-low voltage motion estimation accelerator in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 51: 316-317+616+305. DOI: 10.1109/ISSCC.2008.4523184  0.317
2008 Kaul H, Seo JS, Anders M, Sylvester D, Krishnamurthy R. A robust alternate repeater technique for high performance busses in the multi-core era Proceedings - Ieee International Symposium On Circuits and Systems. 372-375. DOI: 10.1109/ISCAS.2008.4541432  0.584
2008 Anders M, Kaul H, Hansson M, Krishnamurthy R, Borkar S. A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS Esscirc 2008 - Proceedings of the 34th European Solid-State Circuits Conference. 182-185. DOI: 10.1109/ESSCIRC.2008.4681822  0.314
2007 Venkatraman V, Anders M, Kaul H, Burleson W, Krishnamurthy R. A low-swing signaling circuit technique for 65nm on-chip interconnects 2006 Ieee International Systems-On-Chip Conference, Soc. 289-292. DOI: 10.1109/SOCC.2006.283900  0.311
2006 Agarwal A, Hsu SK, Kaul H, Anders MA, Krishnamurthy RK. A dual-supply 4GHz 13fJ/bit/search 64×128b CAM in 65nm CMOS Esscirc 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 303-306. DOI: 10.1109/ESSCIR.2006.307591  0.347
2005 Kaul H, Sylvester D, Anders MA, Krishnamurthy RK. Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1225-1237. DOI: 10.1109/Tvlsi.2005.859589  0.584
2005 Kaul H, Sylvester D, Blaauw D, Mudge T, Austin T. DVS for on-chip bus designs based on timing error correction Proceedings -Design, Automation and Test in Europe, Date '05. 80-85. DOI: 10.1109/DATE.2005.125  0.322
2005 Kaul H. High-performance on-chip interconnect circuit technologies for sub-65nm CMOS Proceedings - Ieee International Soc Conference. 324.  0.355
2005 Kaul H, Sylvester D. A novel buffer circuit for energy efficient signaling in dual-VDD systems Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 462-467.  0.364
2004 Kaul H, Sylvester D. Low-power on-chip communication based on transition-aware global signaling (TAGS) Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 464-476. DOI: 10.1109/Tvlsi.2004.826199  0.556
2004 Kaul H, Sylvester D, Blaauw D. Performance optimization of critical nets through active shielding Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 2417-2435. DOI: 10.1109/Tcsi.2004.838247  0.523
2001 Sylvester D, Kaul H. Power-driven challenges in nanometer design Ieee Design and Test of Computers. 18: 12-22. DOI: 10.1109/54.970420  0.556
2001 Sylvester D, Kaul H. Future performance challenges in nanometer design Proceedings - Design Automation Conference. 3-8.  0.304
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