Parents
Sign in to add mentor| Alain Greiner | grad student | 2008 | UPMC Univ Paris 6 | |
| (Connaissance et synthèse en vue de la conception et la réutilisation de circuits analogiques intégrés) | ||||
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Publications
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| Moursy Y, Zou H, Khalil R, et al. (2017) Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications Ieee Transactions On Power Electronics. 32: 5550-5559 |
| Zou H, Moursy Y, Iskander R, et al. (2016) Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology Ieee Transactions On Circuits and Systems. 63: 2323-2333 |
| Buccella P, Stefanucci C, Zou H, et al. (2016) Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1489-1502 |
| Malak A, Li Y, Iskander R, et al. (2015) Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations Integration. 48: 198-212 |
| Iskander R, LouëRat M, Kaiser A. (2013) Hierarchical sizing and biasing of analog firm intellectual properties Integration. 46: 172-188 |
| Youssef S, Javid F, Dupuis D, et al. (2011) A Python-based layout-aware analog design methodology for nanometric technologies International Design and Test Workshop. 62-67 |
| Iskander R, Louërat M, Kaiser A. (2008) Automatic DC operating point computation and design plan generation for analog IPs Analog Integrated Circuits and Signal Processing. 56: 93-105 |