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Seok-Bum Ko, Ph.D. - Publications

Affiliations: 
2002 University of Rhode Island, Providence, RI, United States 
Area:
Electronics and Electrical Engineering
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66 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Wang Y, Choi EJ, Choi Y, Zhang H, Jin GY, Ko SB. Breast Cancer Classification in Automated Breast Ultrasound Using Multiview Convolutional Neural Network with Transfer Learning. Ultrasound in Medicine & Biology. PMID 32059918 DOI: 10.1016/J.Ultrasmedbio.2020.01.001  0.329
2020 Ahmed S, Baba MI, Bhat SM, Manzoor I, Nafees N, Ko S. Design of reversible universal and multifunctional gate-based 1-bit full adder and full subtractor in quantum-dot cellular automata nanocomputing Journal of Nanophotonics. 14: 36002. DOI: 10.1117/1.Jnp.14.036002  0.403
2020 Yepez J, Ko S. Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks Ieee Transactions On Very Large Scale Integration Systems. 28: 853-863. DOI: 10.1109/Tvlsi.2019.2961602  0.412
2020 Zhang H, Ko S. Design of Power Efficient Posit Multiplier Ieee Transactions On Circuits and Systems Ii-Express Briefs. 67: 861-865. DOI: 10.1109/Tcsii.2020.2980531  0.416
2020 Asadikouhanjani M, Ko S. A Novel Architecture for Early Detection of Negative Output Features in Deep Neural Network Accelerators Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1. DOI: 10.1109/Tcsii.2020.2977015  0.313
2020 Adams E, Venkatachalam S, Ko S. Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders Ieee Transactions On Computers. 69: 468-474. DOI: 10.1109/Tc.2019.2953751  0.454
2020 Zhang H, Chen D, Ko S. New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference Ieee Transactions On Computers. 69: 26-38. DOI: 10.1109/Tc.2019.2936192  0.427
2020 Raj M, Gopalakrishnan L, Ko S. Design and analysis of novel QCA full adder-subtractor International Journal of Electronics Letters. 1-14. DOI: 10.1080/21681724.2020.1726479  0.343
2020 Castro-Zunti RD, Yépez J, Ko S. License plate segmentation and recognition system using deep learning and OpenVINO Iet Intelligent Transport Systems. 14: 119-126. DOI: 10.1049/Iet-Its.2019.0481  0.374
2020 Shahbazi K, Ko S. High throughput and area-efficient FPGA implementation of AES for high-traffic applications Iet Computers and Digital Techniques. DOI: 10.1049/Iet-Cdt.2019.0179  0.344
2020 Majdabadi MM, Shokouhi SB, Ko S. Efficient Hybrid CMOS/Memristor Implementation of Bidirectional Associative Memory Using Passive Weight Array Microelectronics Journal. 98: 104725. DOI: 10.1016/J.Mejo.2020.104725  0.42
2020 Amaranageswarao G, Deivalakshmi S, Ko S. Wavelet based medical image super resolution using cross connected residual-in-dense grouped convolutional neural network Journal of Visual Communication and Image Representation. 70: 102819. DOI: 10.1016/J.Jvcir.2020.102819  0.302
2020 Amaranageswarao G, Deivalakshmi S, Ko S. Blind compression artifact reduction using dense parallel convolutional neural network Signal Processing-Image Communication. 116009. DOI: 10.1016/J.Image.2020.116009  0.396
2020 Amaranageswarao G, Deivalakshmi S, Ko S. Deep dilated and densely connected parallel convolutional groups for compression artifacts reduction Digital Signal Processing. 106: 102804. DOI: 10.1016/J.Dsp.2020.102804  0.382
2020 Wang Y, Zhang H, Chae KJ, Choi Y, Jin GY, Ko S. Novel convolutional neural network architecture for improved pulmonary nodule classification on computed tomography Multidimensional Systems and Signal Processing. 31: 1163-1183. DOI: 10.1007/S11045-020-00703-6  0.361
2020 Majdabadi MM, Ko S. Capsule GAN for robust face super resolution Multimedia Tools and Applications. 1-14. DOI: 10.1007/S11042-020-09489-Y  0.334
2020 Amaranageswarao G, Deivalakshmi S, Ko S. Residual learning based densely connected deep dilated network for joint deblocking and super resolution Applied Intelligence. 50: 2177-2193. DOI: 10.1007/S10489-020-01670-Y  0.369
2020 Velayudham S, Rajagopal S, Ko S. An Improved Low-Power Coding for Serial Network-On-Chip Links Circuits Systems and Signal Processing. 39: 1896-1919. DOI: 10.1007/S00034-019-01231-W  0.417
2019 Venkatachalam S, Adams E, Lee HJ, Ko S. Design and Analysis of Area and Power Efficient Approximate Booth Multipliers Ieee Transactions On Computers. 68: 1697-1703. DOI: 10.1109/Tc.2019.2926275  0.422
2019 Zhang H, Chen D, Ko S. Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support Ieee Transactions On Computers. 68: 1035-1048. DOI: 10.1109/Tc.2019.2895031  0.336
2019 Alagarsamy A, Gopalakrishnan L, Mahilmaran S, Ko S. A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption Ieee Access. 7: 84066-84081. DOI: 10.1109/Access.2019.2925381  0.375
2019 Yépez J, Castro-Zunti RD, Ko S. Deep learning-based embedded license plate localisation system Iet Intelligent Transport Systems. 13: 1569-1578. DOI: 10.1049/Iet-Its.2019.0082  0.448
2019 Wang Y, Shahbazi K, Zhang H, Oh K, Lee J, Ko S. Efficient spiking neural network training and inference with reduced precision memory and computing Iet Computers and Digital Techniques. 13: 397-404. DOI: 10.1049/Iet-Cdt.2019.0115  0.407
2019 Alagarsamy A, Gopalakrishnan L, Ko S. KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC Iet Computers and Digital Techniques. 13: 324-334. DOI: 10.1049/Iet-Cdt.2018.5055  0.417
2019 Raj M, Gopalakrishnan L, Ko S. Fast Quantum-Dot Cellular Automata Adder/Subtractor Using Novel Fault Tolerant Exclusive-or Gate and Full Adder International Journal of Theoretical Physics. 58: 3049-3064. DOI: 10.1007/S10773-019-04184-7  0.381
2018 Jiang Z, Zhang H, Wang Y, Ko SB. Retinal blood vessel segmentation using fully convolutional network with transfer learning. Computerized Medical Imaging and Graphics : the Official Journal of the Computerized Medical Imaging Society. 68: 1-15. PMID 29775951 DOI: 10.1016/J.Compmedimag.2018.04.005  0.312
2018 Venkatachalam S, Ko S. Approximate Sum-of-Products Designs Based on Distributed Arithmetic Ieee Transactions On Very Large Scale Integration Systems. 26: 1604-1608. DOI: 10.1109/Tvlsi.2018.2818980  0.4
2018 Yepez J, Ko S. Improved License Plate Localization Algorithm Based on Morphological Operations Iet Intelligent Transport Systems. 12: 542-549. DOI: 10.1049/Iet-Its.2017.0224  0.375
2018 Zhang H, Chen D, Ko S. High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA Iet Computers and Digital Techniques. 12: 20-29. DOI: 10.1049/Iet-Cdt.2016.0200  0.479
2018 Loi KCC, Ko S. Flexible elliptic curve cryptography coprocessor using scalable finite field arithmetic blocks on FPGAs Microprocessors and Microsystems. 63: 182-189. DOI: 10.1016/J.Micpro.2018.09.003  0.418
2017 Venkatachalam S, Ko S. Design of Power and Area Efficient Approximate Multipliers Ieee Transactions On Very Large Scale Integration Systems. 25: 1782-1786. DOI: 10.1109/Tvlsi.2016.2643639  0.444
2017 Zhang H, Chen D, Ko S. Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA Iet Computers and Digital Techniques. 11: 149-158. DOI: 10.1049/Iet-Cdt.2016.0100  0.459
2017 Jiang Z, Yepez J, An S, Ko S. Fast, accurate and robust retinal vessel segmentation system Biocybernetics and Biomedical Engineering. 37: 412-421. DOI: 10.1016/J.Bbe.2017.04.001  0.335
2016 Kaivani A, Ko S. Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation Ieee Transactions On Very Large Scale Integration Systems. 24: 1208-1211. DOI: 10.1109/Tvlsi.2015.2437999  0.42
2016 Kathirvel S, Jangre R, Ko S. Design of a novel energy efficient topology for maximum magnitude generator Iet Computers and Digital Techniques. 10: 93-101. DOI: 10.1049/Iet-Cdt.2015.0066  0.454
2016 Han L, Zhang H, Ko S. Decimal floating-point fused multiply-add with redundant internal encodings Iet Computers and Digital Techniques. 10: 147-156. DOI: 10.1049/Iet-Cdt.2015.0058  0.454
2015 Loi KCC, Ko SB. Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2753-2756. DOI: 10.1109/Tvlsi.2014.2375640  0.426
2015 Kumar M, Gaur MS, Laxmi V, Daneshtalab M, Zwolinski M, Ko S. Improved adaptive routing for networks-onchip Electronics Letters. 51: 2092-2094. DOI: 10.1049/El.2015.1024  0.361
2015 Han L, Zhang H, Ko SB. Area and power efficient decimal carry-free adder Electronics Letters. 51: 1852-1854. DOI: 10.1049/El.2015.0786  0.476
2015 Kaivani A, Ko SB. Area efficient floating-point FFT butterfly architectures based on multi-operand adders Electronics Letters. 51: 895-897. DOI: 10.1049/El.2015.0342  0.449
2015 Loi KCC, Ko SB. Parallelization of scalable elliptic curve cryptosystem processors in GF(2m) Microprocessors and Microsystems. DOI: 10.1016/J.Micpro.2016.02.013  0.444
2015 Lal C, Laxmi V, Gaur MS, Ko SB. Bandwidth-aware routing and admission control for efficient video streaming over MANETs Wireless Networks. 21: 95-114. DOI: 10.1007/S11276-014-0774-2  0.361
2014 Kaivani A, Han L, Ko SB. Improved design of high-frequency sequential decimal multipliers Electronics Letters. 50: 558-560. DOI: 10.1049/El.2013.2320  0.389
2014 Jin X, Daku B, Ko SB. Improved GPU SIMD control flow efficiency via hybrid warp size mechanism Microprocessors and Microsystems. 38: 717-729. DOI: 10.1016/J.Micpro.2014.06.007  0.406
2014 Swaminathan K, Lakshminarayanan G, Ko SB. Design and verification of an efficient WISHBONE-based network interface for network on chip Computers and Electrical Engineering. 40: 1838-1857. DOI: 10.1016/J.Compeleceng.2014.05.006  0.389
2013 Swaminathan K, Lakshminarayanan G, Ko SB. High speed low power ping pong buffering based network interface for Network on Chip Journal of Low Power Electronics. 9: 322-331. DOI: 10.1166/Jolpe.2013.1265  0.384
2013 Han L, Ko SB. High-speed parallel decimal multiplication with redundant internal encodings Ieee Transactions On Computers. 62: 956-968. DOI: 10.1109/Tc.2012.35  0.463
2013 Loi KCC, Ko SB. High performance scalable elliptic curve cryptosystem processor for Koblitz curves Microprocessors and Microsystems. 37: 394-406. DOI: 10.1016/J.Micpro.2013.03.003  0.407
2013 Vennila C, Patel AK, Lakshminarayanan G, Ko SB. Dynamic partial reconfigurable Viterbi decoder for wireless standards Computers and Electrical Engineering. 39: 164-174. DOI: 10.1016/J.Compeleceng.2012.12.009  0.439
2013 Choi Y, Zhang Q, Ko S. Noninvasive cuffless blood pressure estimation using pulse transit time and Hilbert-Huang transform Computers & Electrical Engineering. 39: 103-111. DOI: 10.1016/J.Compeleceng.2012.09.005  0.302
2013 Kaivani A, Ko SB. Decimal SRT square root: Algorithm and architecture Circuits, Systems, and Signal Processing. 32: 2137-2150. DOI: 10.1007/S00034-013-9586-3  0.423
2012 Chen D, Han L, Choi Y, Ko SB. Improved decimal floating-point logarithmic converter based on selection by rounding Ieee Transactions On Computers. 61: 607-621. DOI: 10.1109/Tc.2011.43  0.487
2012 Chen D, Han L, Ko SB. Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture Iet Computers and Digital Techniques. 6: 277-289. DOI: 10.1049/Iet-Cdt.2011.0089  0.46
2012 Chen D, Ko SB. A dynamic non-uniform segmentation method for first-order polynomial function evaluation Microprocessors and Microsystems. 36: 324-332. DOI: 10.1016/J.Micpro.2012.02.016  0.367
2012 Vennila C, Lakshminarayanan G, Ko SB. Dynamic partial reconfigurable FFT for OFDM based communication systems Circuits, Systems, and Signal Processing. 31: 1049-1066. DOI: 10.1007/S00034-011-9367-9  0.439
2012 Chen D, Ko SB. A novel decimal logarithmic converter based on first-order polynomial approximation Circuits, Systems, and Signal Processing. 31: 1179-1190. DOI: 10.1007/S00034-011-9365-Y  0.388
2011 Loi KCC, Ko SB. Improvements on the design and implementation of DVB-S2 LDPC decoders Computers and Electrical Engineering. 37: 1137-1146. DOI: 10.1016/J.Compeleceng.2011.06.005  0.378
2010 Zhang Y, Chen D, Choi Y, Chen L, Ko SB. A high performance ECC hardware implementation with instruction-level parallelism over GF(2163) Microprocessors and Microsystems. 34: 228-236. DOI: 10.1016/J.Micpro.2010.04.006  0.442
2010 Wahid KA, Islam MA, Shimu SS, Lee MH, Ko SB. Hybrid architecture and VLSI implementation of the cosine-fourier-haar transforms Circuits, Systems, and Signal Processing. 29: 1193-1205. DOI: 10.1007/S00034-010-9200-X  0.381
2009 Dinh A, Shi Y, Teng D, Ralhan A, Chen L, Dal Bello-Haas V, Basran J, Ko SB, McCrowsky C. A fall and near-fall assessment and evaluation system. The Open Biomedical Engineering Journal. 3: 1-7. PMID 19662151 DOI: 10.2174/1874120700903010001  0.332
2009 Ko SB, Lee Y, Choi Y, Ho Lee M. Performance analysis of bit-width reduced floating-point arithmetic units in FPGAs: A case study of neural network-based face detector Eurasip Journal On Embedded Systems. 2009. DOI: 10.1155/2009/258921  0.379
2008 Muma K, Chen D, Choi Y, Dodds D, Lee MH, Ko S. Combining ESOP minimization with BDD-based decomposition for improved FPGA synthesis Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique Et Informatique. 33: 177-182. DOI: 10.1109/Cjece.2008.4721635  0.408
2008 Malik A, Chen D, Choi Y, Lee M, Ko S. Design tradeoff analysis of floating-point adders in FPGAs Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique Et Informatique. 33: 169-175. DOI: 10.1109/Cjece.2008.4721634  0.428
2004 Ko SB, Lo JC. Efficient realization of parity prediction functions in FPGAs Journal of Electronic Testing: Theory and Applications (Jetta). 20: 489-499. DOI: 10.1023/B:Jett.0000042513.15382.E7  0.545
2004 Ko SB. Area minimization of exclusive-OR intensive circuits in FPGAs Journal of Electronic Testing: Theory and Applications (Jetta). 20: 661-665. DOI: 10.1007/S10677-004-4253-1  0.407
2003 Ko SB. A New Partitioning Method for LUT-based FPGAs Canadian Conference On Electrical and Computer Engineering. 1: 103-106.  0.33
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