| Year |
Citation |
Score |
| 2020 |
Assem P, Liu W, Lei Y, Hanumolu PK, Pilawa-Podgurski RCN. Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS Ieee Journal of Solid-State Circuits. 55: 2513-2528. DOI: 10.1109/Jssc.2020.3004256 |
0.519 |
|
| 2020 |
Hanumolu PK. New Associate Editors Ieee Journal of Solid-State Circuits. 55: 1439-1440. DOI: 10.1109/Jssc.2020.2988136 |
0.454 |
|
| 2020 |
Kim D, Ahmed MG, Choi W, Elkholy A, Hanumolu PK. A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS Ieee Journal of Solid-State Circuits. 55: 2196-2205. DOI: 10.1109/Jssc.2020.2978138 |
0.575 |
|
| 2020 |
Khashaba A, Elkholy A, Megawer KM, Ahmed MG, Hanumolu PK. A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques Ieee Journal of Solid-State Circuits. 55: 592-601. DOI: 10.1109/Jssc.2019.2951384 |
0.651 |
|
| 2019 |
Wang T, Griffith D, Ahmed MG, Zhu J, Wei D, Elkholy A, Elmallah A, Hanumolu PK. A 6 $\mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation Ieee Transactions On Circuits and Systems Ii-Express Briefs. 66: 1297-1301. DOI: 10.1109/Tcsii.2018.2884657 |
0.422 |
|
| 2019 |
Sevuktekin NC, Varshney LR, Hanumolu PK, Singer AC. Signal Processing Foundations for Time-Based Signal Representations: Neurobiological Parallels to Engineered Systems Designed for Energy Efficiency or Hardware Simplicity Ieee Signal Processing Magazine. 36: 38-50. DOI: 10.1109/Msp.2019.2929466 |
0.33 |
|
| 2019 |
Megawer KM, Pal N, Elkholy A, Ahmed MG, Khashaba A, Griffith D, Hanumolu PK. A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection Ieee Journal of Solid-State Circuits. 54: 3257-3268. DOI: 10.1109/Jssc.2019.2936296 |
0.439 |
|
| 2019 |
Zhu J, Choi W, Hanumolu PK. A 0.016 mm 2 0.26- $\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS Ieee Journal of Solid-State Circuits. 54: 2186-2194. DOI: 10.1109/Jssc.2019.2915021 |
0.613 |
|
| 2019 |
Elkholy A, Coombs D, Nandwana RK, Elmallah A, Hanumolu PK. A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler Ieee Journal of Solid-State Circuits. 54: 2049-2058. DOI: 10.1109/Jssc.2019.2904884 |
0.649 |
|
| 2019 |
Kim D, Choi W, Elkholy A, Kenney J, Hanumolu PK. A 15-Gb/s Sub-Baud-Rate Digital CDR Ieee Journal of Solid-State Circuits. 54: 685-695. DOI: 10.1109/Jssc.2018.2885540 |
0.554 |
|
| 2019 |
Ahmed MG, Huynh TN, Williams C, Wang Y, Hanumolu PK, Rylyakov A. 34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers Ieee Journal of Solid-State Circuits. 54: 834-844. DOI: 10.1109/Jssc.2018.2882265 |
0.519 |
|
| 2019 |
Megawer KM, Elkholy A, Ahmed MG, Elmallah A, Hanumolu PK. Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers Ieee Journal of Solid-State Circuits. 54: 65-74. DOI: 10.1109/Jssc.2018.2872539 |
0.622 |
|
| 2018 |
Ordentlich O, Tabak G, Hanumolu PK, Singer AC, Wornell GW. A Modulo-Based Architecture for Analog-to-Digital Conversion. Ieee Journal of Selected Topics in Signal Processing. 12: 825-840. PMID 33747333 DOI: 10.1109/jstsp.2018.2863189 |
0.376 |
|
| 2018 |
Ordentlich O, Tabak G, Hanumolu PK, Singer AC, Wornell GW. A Modulo-Based Architecture for Analog-to-Digital Conversion Ieee Journal of Selected Topics in Signal Processing. 12: 825-840. DOI: 10.1109/Jstsp.2018.2863189 |
0.478 |
|
| 2018 |
Elkholy A, Saxena S, Shu G, Elshazly A, Hanumolu PK. Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers Ieee Journal of Solid-State Circuits. 53: 1806-1817. DOI: 10.1109/Jssc.2018.2817602 |
0.803 |
|
| 2018 |
Elkholy A, Elmallah A, Ahmed MG, Hanumolu PK. A 6.75–8.25-GHz −250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier Ieee Journal of Solid-State Circuits. 53: 1818-1829. DOI: 10.1109/Jssc.2018.2810184 |
0.487 |
|
| 2018 |
Choi W, Shu G, Talegaonkar M, Liu Y, Wei D, Benini L, Hanumolu PK. A 0.45–0.7 V 1–6 Gb/s 0.29–0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation Ieee Journal of Solid-State Circuits. 53: 884-895. DOI: 10.1109/Jssc.2017.2786716 |
0.553 |
|
| 2018 |
Wei D, Anand T, Shu G, Schutt-Aine JE, Hanumolu PK. A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects Ieee Journal of Solid-State Circuits. 53: 873-883. DOI: 10.1109/Jssc.2017.2782082 |
0.49 |
|
| 2018 |
Kim SJ, Choi W, Pilawa-Podgurski R, Hanumolu PK. A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes Ieee Journal of Solid-State Circuits. 53: 814-824. DOI: 10.1109/Jssc.2017.2776298 |
0.475 |
|
| 2018 |
Ahmed MG, Talegaonkar M, Elkholy A, Shu G, Elmallah A, Rylyakov A, Hanumolu PK. A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS Ieee Journal of Solid-State Circuits. 53: 445-457. DOI: 10.1109/Jssc.2017.2757008 |
0.484 |
|
| 2017 |
Nandwana RK, Saxena S, Elshazly A, Mayaram K, Hanumolu PK. A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 283-295. DOI: 10.1109/Tcsi.2016.2609855 |
0.793 |
|
| 2017 |
Talegaonkar M, Anand T, Elkholy A, Elshazly A, Nandwana RK, Saxena S, Young B, Choi W, Hanumolu PK. A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS Ieee Journal of Solid-State Circuits. 52: 2306-2320. DOI: 10.1109/Jssc.2017.2718670 |
0.808 |
|
| 2017 |
Saxena S, Shu G, Nandwana RK, Talegaonkar M, Elkholy A, Anand T, Choi W, Hanumolu PK. A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver Ieee Journal of Solid-State Circuits. 52: 1399-1411. DOI: 10.1109/Jssc.2016.2645738 |
0.621 |
|
| 2017 |
Zhu J, Nandwana RK, Shu G, Elkholy A, Kim SJ, Hanumolu PK. A 0.0021 mm 2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS Ieee Journal of Solid-State Circuits. 52: 8-20. DOI: 10.1109/Jssc.2016.2598768 |
0.615 |
|
| 2016 |
Anand T, Makinwa KAA, Hanumolu PK. A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity Ieee Journal of Solid-State Circuits. 51: 2651-2663. DOI: 10.1109/Jssc.2016.2598765 |
0.425 |
|
| 2016 |
Elkholy A, Saxena S, Nandwana RK, Elshazly A, Hanumolu PK. A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2016.2557807 |
0.822 |
|
| 2016 |
Shu G, Choi WS, Saxena S, Talegaonkar M, Anand T, Elkholy A, Elshazly A, Hanumolu PK. A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition Ieee Journal of Solid-State Circuits. 51: 428-439. DOI: 10.1109/Jssc.2015.2497963 |
0.802 |
|
| 2016 |
Shu G, Choi WS, Saxena S, Kim SJ, Talegaonkar M, Nandwana R, Elkholy A, Wei D, Nandi T, Hanumolu PK. 23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 398-399. DOI: 10.1109/ISSCC.2016.7418075 |
0.403 |
|
| 2016 |
Zhu J, Nandwana RK, Shu G, Elkholy A, Kim SJ, Hanumolu PK. 19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 338-340. DOI: 10.1109/ISSCC.2016.7418045 |
0.608 |
|
| 2016 |
Elkholy A, Elmallah A, Elzeftawi M, Chang K, Hanumolu PK. 10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 192-193. DOI: 10.1109/ISSCC.2016.7417972 |
0.488 |
|
| 2015 |
Reddy K, Dey S, Rao S, Young B, Prabha P, Hanumolu PK. A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2015: C256-C257. DOI: 10.1109/VLSIC.2015.7231278 |
0.39 |
|
| 2015 |
Elkholy A, Talegaonkar M, Anand T, Hanumolu PK. Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers Ieee Journal of Solid-State Circuits. 50: 3160-3174. DOI: 10.1109/Jssc.2015.2478449 |
0.617 |
|
| 2015 |
Anand T, Talegaonkar M, Elkholy A, Saxena S, Elshazly A, Hanumolu PK. A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2015.2470553 |
0.731 |
|
| 2015 |
Kim SJ, Nandwana RK, Khan Q, Pilawa-Podgurski RCN, Hanumolu PK. A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator Ieee Journal of Solid-State Circuits. 50: 2814-2824. DOI: 10.1109/Jssc.2015.2456884 |
0.781 |
|
| 2015 |
Prabha P, Kim SJ, Reddy K, Rao S, Griesert N, Rao A, Winter G, Hanumolu PK. A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2015.2414428 |
0.525 |
|
| 2015 |
Choi WS, Anand T, Shu G, Elshazly A, Hanumolu PK. A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links Ieee Journal of Solid-State Circuits. 50: 737-748. DOI: 10.1109/Jssc.2015.2390613 |
0.774 |
|
| 2015 |
Nandwana RK, Anand T, Saxena S, Kim SJ, Talegaonkar M, Elkholy A, Choi WS, Elshazly A, Hanumolu PK. A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method Ieee Journal of Solid-State Circuits. 50: 882-895. DOI: 10.1109/Jssc.2014.2385756 |
0.776 |
|
| 2015 |
Elkholy A, Anand T, Choi WS, Elshazly A, Hanumolu PK. A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC Ieee Journal of Solid-State Circuits. 50: 867-881. DOI: 10.1109/Jssc.2014.2385753 |
0.804 |
|
| 2015 |
Kim SJ, Khan Q, Talegaonkar M, Elshazly A, Rao A, Griesert N, Winter G, McIntyre W, Hanumolu PK. High Frequency Buck Converter Design Using Time-Based Control Techniques Ieee Journal of Solid-State Circuits. 50: 990-1001. DOI: 10.1109/Jssc.2014.2378216 |
0.841 |
|
| 2015 |
Kim SJ, Nandwana RK, Khan Q, Pilawa-Podgurski R, Hanumolu PK. A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm<sup>2</sup> 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 216-217. DOI: 10.1109/ISSCC.2015.7063003 |
0.499 |
|
| 2015 |
Elkholy A, Talegaonkar M, Anand T, Hanumolu PK. A 6.75-to-8.25GHz 2.25mW 190fs<inf>rms</inf> integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 188-189. DOI: 10.1109/ISSCC.2015.7062989 |
0.537 |
|
| 2015 |
Choi WS, Shu G, Talegaonkar M, Liu Y, Wei D, Benini L, Hanumolu PK. A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 66-67. DOI: 10.1109/ISSCC.2015.7062928 |
0.558 |
|
| 2015 |
Anand T, Talegaonkar M, Elkholy A, Saxena S, Elshazly A, Hanumolu PK. A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 64-65. DOI: 10.1109/ISSCC.2015.7062927 |
0.668 |
|
| 2015 |
Elkholy A, Saxena S, Nandwana RK, Elshazly A, Hanumolu PK. A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter Proceedings of the Custom Integrated Circuits Conference. 2015. DOI: 10.1109/CICC.2015.7338376 |
0.786 |
|
| 2014 |
Nandwana RK, Anand T, Saxena S, Kim SJ, Talegaonkar M, Elkholy A, Choi WS, Elshazly A, Hanumolu PK. A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. DOI: 10.1109/VLSIC.2014.6858446 |
0.768 |
|
| 2014 |
Khan Q, Kim SJ, Talegaonkar M, Elshazly A, Rao A, Griesert N, Winter G, McIntyre W, Hanumolu PK. A 10-25MHz, 600mA buck converter using time-based PID compensator with 2μA/MHz quiescent current, 94% peak efficiency, and 1MHz BW Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. DOI: 10.1109/VLSIC.2014.6858439 |
0.703 |
|
| 2014 |
Young B, Reddy K, Rao S, Elshazly A, Anand T, Hanumolu PK. A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. DOI: 10.1109/VLSIC.2014.6858395 |
0.749 |
|
| 2014 |
Talegaonkar M, Anand T, Elkholy A, Elshazly A, Nandwana RK, Saxena S, Young B, Choi W, Hanumolu PK. A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. DOI: 10.1109/VLSIC.2014.6858392 |
0.788 |
|
| 2014 |
Elkholy A, Anand T, Choi WS, Elshazly A, Hanumolu PK. A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. DOI: 10.1109/VLSIC.2014.6858391 |
0.761 |
|
| 2014 |
Nagata M, Breems LJ, Samori C, Mattisson S, Hanumolu PK. Introduction to the special issue on the 2014 IEEE international solid-state circuits conferences (ISSCC) Ieee Journal of Solid-State Circuits. 49: 2743-2747. DOI: 10.1109/Jssc.2014.2366411 |
0.323 |
|
| 2014 |
Talegaonkar M, Elshazly A, Reddy K, Prabha P, Anand T, Hanumolu PK. An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS Ieee Journal of Solid-State Circuits. 49: 2228-2242. DOI: 10.1109/Jssc.2014.2348317 |
0.748 |
|
| 2014 |
Anand T, Elshazly A, Talegaonkar M, Young B, Hanumolu PK. A 5 Gb/s, 10 ns Power-On-Time, 36 μW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2014.2345764 |
0.742 |
|
| 2014 |
Saxena S, Nandwana RK, Hanumolu PK. A 5 Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis Ieee Journal of Solid-State Circuits. 49: 1827-1836. DOI: 10.1109/Jssc.2014.2317142 |
0.508 |
|
| 2014 |
Elshazly A, Rao S, Young B, Hanumolu PK. A noise-shaping time-to-digital converter using switched-ring oscillators - Analysis, design, and measurement techniques Ieee Journal of Solid-State Circuits. 49: 1184-1197. DOI: 10.1109/Jssc.2014.2305651 |
0.796 |
|
| 2014 |
Shu G, Saxena S, Choi WS, Talegaonkar M, Inti R, Elshazly A, Young B, Hanumolu PK. A reference-less clock and data recovery circuit using phase-rotating phase-locked loop Ieee Journal of Solid-State Circuits. 49: 1036-1047. DOI: 10.1109/Jssc.2013.2296152 |
0.865 |
|
| 2014 |
Rao S, Reddy K, Young B, Hanumolu PK. A deterministic digital background calibration technique for VCO-based ADCs Ieee Journal of Solid-State Circuits. 49: 950-960. DOI: 10.1109/Jssc.2013.2293753 |
0.623 |
|
| 2014 |
Elkholy A, Elshazly A, Saxena S, Shu G, Hanumolu PK. 15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 272-273. DOI: 10.1109/ISSCC.2014.6757431 |
0.798 |
|
| 2014 |
Shu G, Choi WS, Saxena S, Anand T, Elshazly A, Hanumolu PK. 8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 150-151. DOI: 10.1109/ISSCC.2014.6757377 |
0.761 |
|
| 2013 |
Hanumolu PK, Moon U. Shannon Limit of Collegiality Ieee Solid-State Circuits Magazine. 5: 14-14. DOI: 10.1109/Mssc.2013.2255758 |
0.305 |
|
| 2013 |
Elshazly A, Inti R, Young B, Hanumolu PK. Clock multiplication techniques using digital multiplying delay-locked loops Ieee Journal of Solid-State Circuits. 48: 1416-1428. DOI: 10.1109/Jssc.2013.2254552 |
0.879 |
|
| 2013 |
Zanbaghi R, Hanumolu PK, Fiez TS. An 80-dB DR, 7.2-MHz bandwidth single opamp biquad based CT Δ Σ modulator dissipating 13.7-mW Ieee Journal of Solid-State Circuits. 48: 487-501. DOI: 10.1109/Jssc.2012.2221194 |
0.525 |
|
| 2013 |
Anand T, Talegaonkar M, Elshazly A, Young B, Hanumolu PK. A 2.5GHz 2.2mW/25μW on/off-state power 2psrms-long-term- jitter digital clock multiplier with 3-reference-cycles power-on time Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 56: 256-257. DOI: 10.1109/ISSCC.2013.6487724 |
0.732 |
|
| 2013 |
Saxena S, Nandwana RK, Hanumolu PK. A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2013.6658403 |
0.421 |
|
| 2013 |
Rao S, Reddy K, Young B, Hanumolu PK. A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. |
0.497 |
|
| 2013 |
Choi WS, Anand T, Shu G, Hanumolu PK. A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. |
0.427 |
|
| 2013 |
Nandwana RK, Saxena S, Elshazly A, Mayaram K, Hanumolu PK. A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. |
0.755 |
|
| 2013 |
Shu G, Saxena S, Choi WS, Talegaonkar M, Inti R, Elshazly A, Young B, Hanumolu PK. A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. |
0.845 |
|
| 2012 |
Elshazly A, Inti R, Talegaonkar M, Hanumolu PK. A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 188-189. DOI: 10.1109/VLSIC.2012.6243853 |
0.858 |
|
| 2012 |
Khan Q, Elshazly A, Rao S, Inti R, Hanumolu PK. A 900mA 93% efficient 50μA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 182-183. DOI: 10.1109/VLSIC.2012.6243850 |
0.824 |
|
| 2012 |
Sasidhar N, Gubbins D, Hanumolu PK, Moon UK. Rail-to-rail input pipelined ADC incorporating multistage signal mapping Ieee Transactions On Circuits and Systems Ii: Express Briefs. 59: 558-562. DOI: 10.1109/Tcsii.2012.2208668 |
0.502 |
|
| 2012 |
Zaliasl S, Saxena S, Hanumolu PK, Mayaram K, Fiez TS. A 12.5-bit 4 MHz 13.8 mW MASH Δ Σ modulator with multirated VCO-based ADC Ieee Transactions On Circuits and Systems I: Regular Papers. 59: 1604-1613. DOI: 10.1109/Tcsi.2012.2206506 |
0.602 |
|
| 2012 |
Drost B, Talegaonkar M, Hanumolu PK. Analog filter design using ring oscillator integrators Ieee Journal of Solid-State Circuits. 47: 3120-3129. DOI: 10.1109/Jssc.2012.2225738 |
0.568 |
|
| 2012 |
Reddy K, Rao S, Inti R, Young B, Elshazly A, Talegaonkar M, Hanumolu PK. A 16-mW 78-dB SNDR 10-MHz BW CT Δσ ADC Using Residue-Cancelling VCO-Based Quantizer Ieee Journal of Solid-State Circuits. 47: 2916-2927. DOI: 10.1109/Jssc.2012.2218062 |
0.845 |
|
| 2012 |
Elshazly A, Rao S, Young B, Hanumolu PK. A 13b 315fs rms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 464-465. DOI: 10.1109/ISSCC.2012.6177092 |
0.768 |
|
| 2012 |
Drost B, Talegaonkar M, Hanumolu PK. A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4 th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 360-361. DOI: 10.1109/ISSCC.2012.6177051 |
0.529 |
|
| 2012 |
Elshazly A, Inti R, Young B, Hanumolu PK. A 1.5GHz 890μW digital MDLL with 400fs rms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 242-243. DOI: 10.1109/ISSCC.2012.6176993 |
0.868 |
|
| 2012 |
Reddy K, Rao S, Inti R, Young B, Elshazly A, Talegaonkar M, Hanumolu PK. A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 152-153. DOI: 10.1109/ISSCC.2012.6176955 |
0.872 |
|
| 2012 |
Tong T, Yu W, Hanumolu PK, Temes GC. Calibration technique for SAR analog-to-digital converters Analog Integrated Circuits and Signal Processing. 73: 301-309. DOI: 10.1007/S10470-012-9851-6 |
0.39 |
|
| 2012 |
Tong T, Hanumolu PK, Temes GC. A semi-synchronous SAR ADC Analog Integrated Circuits and Signal Processing. 71: 407-410. DOI: 10.1007/S10470-011-9769-4 |
0.376 |
|
| 2011 |
Wang Y, Hanumolu PK, Temes GC. Design techniques for wideband discrete-time delta-sigma ADCs with extra loop delay Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1518-1530. DOI: 10.1109/Tcsi.2011.2143110 |
0.478 |
|
| 2011 |
Vytyaz I, Hanumolu PK, Moon UK, Mayaram K. Design-oriented analysis of circuits with equality constraints Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1089-1098. DOI: 10.1109/Tcsi.2010.2090570 |
0.36 |
|
| 2011 |
Yin W, Inti R, Elshazly A, Talegaonkar M, Young B, Hanumolu PK. A TDC-less 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery Ieee Journal of Solid-State Circuits. 46: 3163-3173. DOI: 10.1109/JSSC.2011.2168873 |
0.851 |
|
| 2011 |
Inti R, Yin W, Elshazly A, Sasidhar N, Hanumolu PK. A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance Ieee Journal of Solid-State Circuits. 46: 3150-3162. DOI: 10.1109/JSSC.2011.2168872 |
0.85 |
|
| 2011 |
Rao S, Khan Q, Bang S, Swank D, Rao A, McIntyre W, Hanumolu PK. A 1.2-A buck-boost LED driver with on-chip error averaged senseFET-based current sensing technique Ieee Journal of Solid-State Circuits. 46: 2772-2783. DOI: 10.1109/Jssc.2011.2162921 |
0.701 |
|
| 2011 |
Elshazly A, Inti R, Yin W, Young B, Hanumolu PK. A 0.4-to-3 GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration Ieee Journal of Solid-State Circuits. 46: 2759-2771. DOI: 10.1109/Jssc.2011.2162912 |
0.87 |
|
| 2011 |
Hanumolu PK, Harjani R, Loke ALS. Introduction to the special issue on the 2010 IEEE custom integrated circuits conference Ieee Journal of Solid-State Circuits. 46: 1770-1771. DOI: 10.1109/Jssc.2011.2159639 |
0.466 |
|
| 2011 |
Yin W, Inti R, Elshazly A, Young B, Hanumolu PK. A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking Ieee Journal of Solid-State Circuits. 46: 1870-1880. DOI: 10.1109/Jssc.2011.2157259 |
0.876 |
|
| 2011 |
Yin W, Inti R, Elshazly A, Hanumolu PK. A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 440-441. DOI: 10.1109/ISSCC.2011.5746388 |
0.823 |
|
| 2011 |
Inti R, Yin W, Elshazly A, Sasidhar N, Hanumolu PK. A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 438-439. DOI: 10.1109/ISSCC.2011.5746387 |
0.837 |
|
| 2011 |
Inti R, Elshazly A, Young B, Yin W, Kossel M, Toifl T, Hanumolu PK. A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 152-153. DOI: 10.1109/ISSCC.2011.5746260 |
0.829 |
|
| 2011 |
Elshazly A, Inti R, Yin W, Young B, Hanumolu PK. A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 92-93. DOI: 10.1109/ISSCC.2011.5746233 |
0.871 |
|
| 2011 |
Khan Q, Rao S, Swank D, Rao A, McIntyre W, Bang S, Hanumolu PK. A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control European Solid-State Circuits Conference. 439-442. DOI: 10.1109/ESSCIRC.2011.6045001 |
0.41 |
|
| 2011 |
Yang B, Drost B, Rao S, Hanumolu PK. A high-PSR LDO using a feedforward supply-noise cancellation technique Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055409 |
0.5 |
|
| 2011 |
Talegaonkar M, Inti R, Hanumolu PK. Digital clock and data recovery circuit design: Challenges and tradeoffs Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055346 |
0.781 |
|
| 2011 |
Agrawal A, Hanumolu PK, Wei GY. Area efficient phase calibration of a 1.6 GHz multiphase DLL Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055345 |
0.425 |
|
| 2011 |
Asl SZ, Saxena S, Hanumolu PK, Mayaram K, Fiez TS. A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055290 |
0.474 |
|
| 2011 |
Lee S, Chae J, Aniya M, Takeuchi S, Hamashita K, Hanumolu PK, Temes GC. A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055289 |
0.489 |
|
| 2011 |
Rao S, Young B, Elshazly A, Yin W, Sasidhar N, Hanumolu PK. A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 270-271. |
0.737 |
|
| 2010 |
Arakali A, Gondi S, Hanumolu PK. Analysis and design techniques for supply-noise mitigation in phase-locked loops Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 2880-2889. DOI: 10.1109/Tcsi.2010.2052507 |
0.844 |
|
| 2010 |
Carusone AC, Hanumolu PK, Harjani R. Introduction to the special issue on the IEEE 2009 custom integrated circuits conference Ieee Journal of Solid-State Circuits. 45: 1425. DOI: 10.1109/Jssc.2010.2050020 |
0.421 |
|
| 2010 |
Gubbins D, Lee B, Hanumolu PK, Moon UK. Continuous-time input pipeline ADCs Ieee Journal of Solid-State Circuits. 45: 1456-1468. DOI: 10.1109/Jssc.2010.2048137 |
0.463 |
|
| 2010 |
Young B, Kwon S, Elshazly A, Hanumolu PK. A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617612 |
0.784 |
|
| 2010 |
Yin W, Inti R, Hanumolu PK. A 1.6mW 1.6ps-rms-Jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617611 |
0.822 |
|
| 2010 |
Chae J, Lee S, Aniya M, Takeuchi S, Hamashita K, Hanumolu PK, Temes GC. A 63 dB 16 mW 20 MHz BW double-sampled ΔΣ analog-to-digital converter with an embedded-adder quantizer Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617594 |
0.489 |
|
| 2010 |
Bang S, Swank D, Rao A, McIntyre W, Khan Q, Hanumolu PK. A 1.2A 2MHz tri-mode buck-boost LED driver with feed-forward duty cycle correction Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617443 |
0.342 |
|
| 2010 |
Young B, Hanumolu PK. Phase-locked loop based delta-sigma ADC Electronics Letters. 46: 403-404. DOI: 10.1049/El.2010.2873 |
0.601 |
|
| 2009 |
Vytyaz I, Lee DC, Hanumolu PK, Moon UK, Mayaram K. Automated design and optimization of low-noise oscillators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 609-622. DOI: 10.1109/Tcad.2009.2014808 |
0.475 |
|
| 2009 |
Agrawal A, Liu A, Hanumolu PK, Wei GY. An 8× 5 Gb/s parallel receiver with collaborative timing recovery Ieee Journal of Solid-State Circuits. 44: 3120-3130. DOI: 10.1109/Jssc.2009.2033399 |
0.488 |
|
| 2009 |
Sasidhar N, Kook YJ, Takeuchi S, Hamashita K, Takasuka K, Hanumolu PK, Moon UK. A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback Ieee Journal of Solid-State Circuits. 44: 2392-2401. DOI: 10.1109/Jssc.2009.2025408 |
0.531 |
|
| 2009 |
Kim MG, Hanumolu PK, Moon UK. A 10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme Ieee Journal of Solid-State Circuits. 44: 2348-2355. DOI: 10.1109/Jssc.2009.2023158 |
0.473 |
|
| 2009 |
Arakali A, Gondi S, Hanumolu PK. Low-power supply-regulation techniques for ring oscillators in phase-locked loops using a split-tuned architecture Ieee Journal of Solid-State Circuits. 44: 2169-2180. DOI: 10.1109/Jssc.2009.2022916 |
0.863 |
|
| 2009 |
Wu T, Hanumolu PK, Mayaram K, Moon UK. Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers Ieee Journal of Solid-State Circuits. 44: 427-435. DOI: 10.1109/Jssc.2008.2010792 |
0.532 |
|
| 2009 |
Kwon S, Hanumolu PK, Kim SH, Lee SN, You SB, Park HJ, Kim JW, Moon UK. An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing Proceedings of the Custom Integrated Circuits Conference. 171-174. DOI: 10.1109/CICC.2009.5280871 |
0.467 |
|
| 2009 |
Sasidhar N, Inti R, Hanumolu PK. Low-noise self-referenced CMOS oscillator Electronics Letters. 45: 920-921. DOI: 10.1049/El.2009.1342 |
0.822 |
|
| 2009 |
Weaver S, Hershberg B, Hanumolu PK, Moon UK. A multiplexer-based digital passive linear counter (PLINCO) 2009 16th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2009. 607-610. DOI: 10.1007/S10470-012-9862-3 |
0.425 |
|
| 2008 |
Kim MG, Ahn GC, Hanumolu PK, Lee SH, Kim SH, You SB, Kim JW, Temes GC, Moon UK. A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC Ieee Journal of Solid-State Circuits. 43: 1195-1205. DOI: 10.1109/Jssc.2008.920329 |
0.519 |
|
| 2008 |
Hanumolu PK, Wei GY, Moon UK. A wide-tracking range clock and data recovery circuit Ieee Journal of Solid-State Circuits. 43: 425-438. DOI: 10.1109/Jssc.2007.914290 |
0.606 |
|
| 2008 |
Hanumolu PK, Kratyuk V, Wei GY, Moon UK. A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter Ieee Journal of Solid-State Circuits. 43: 414-423. DOI: 10.1109/Jssc.2007.914287 |
0.581 |
|
| 2008 |
Agrawal A, Hanumolu PK, Wei GY. An 8×3.2Gb/s parallel receiver with collaborative timing recovery Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 51. DOI: 10.1109/ISSCC.2008.4523260 |
0.32 |
|
| 2008 |
Arakali A, Talebbeydokthi N, Gondi S, Hanumolu PK. Supply-noise mitigation techniques in phase-locked loops Esscirc 2008 - Proceedings of the 34th European Solid-State Circuits Conference. 374-377. DOI: 10.1109/ESSCIRC.2008.4681870 |
0.841 |
|
| 2008 |
Kurahashi P, Hanumolu PK, Moon UK. A 1V downconversion filter using duty-cycle controlled bandwidth tuning Proceedings of the Custom Integrated Circuits Conference. 707-710. DOI: 10.1109/CICC.2008.4672185 |
0.33 |
|
| 2008 |
Vytyaz I, Carnes J, Wu T, Hanumolu PK, Moon UK, Mayaram K. Noise tolerant oscillator design using perturbation projection vector analysis Proceedings of the Custom Integrated Circuits Conference. 695-698. DOI: 10.1109/CICC.2008.4672181 |
0.368 |
|
| 2008 |
Agrawal A, Hanumolu PK, Wei GY. A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction Proceedings of the Custom Integrated Circuits Conference. 459-462. DOI: 10.1109/CICC.2008.4672120 |
0.393 |
|
| 2008 |
Arakali A, Gondi S, Hanumolu PK. A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB Proceedings of the Custom Integrated Circuits Conference. 443-446. DOI: 10.1109/CICC.2008.4672116 |
0.847 |
|
| 2008 |
Gubbins D, Lee B, Hanumolu PK, Moon UK. A continuous-time input pipeline ADC Proceedings of the Custom Integrated Circuits Conference. 169-172. DOI: 10.1109/CICC.2008.4672050 |
0.405 |
|
| 2008 |
Ahn GC, Kim MG, Hanumolu PK, Moon UK. A 1V 10b 30MSPS switched-RC pipelined ADC Proceedings of the Custom Integrated Circuits Conference. 325-328. DOI: 10.1109/CICC.2007.4405744 |
0.414 |
|
| 2008 |
Kratyuk V, Hanumolu PK, Mayaram K, Moon UK. A 0.6GHz to 2GHz digital PLL with wide tracking range Proceedings of the Custom Integrated Circuits Conference. 305-308. DOI: 10.1109/CICC.2007.4405739 |
0.441 |
|
| 2008 |
Kim MG, Kratyuk V, Hanumolu PK, Ahn GC, Kwon S, Moon UK. An 8mW 10b 50MS/s pipelined ADC using 25dB opamp Proceedings of 2008 Ieee Asian Solid-State Circuits Conference, a-Sscc 2008. 49-52. DOI: 10.1109/ASSCC.2008.4708726 |
0.446 |
|
| 2007 |
Kratyuk V, Hanumolu PK, Moon UK, Mayaram K. A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 247-251. DOI: 10.1109/Tcsii.2006.889443 |
0.46 |
|
| 2007 |
Vytyaz I, Lee DC, Hanumolu PK, Moon UK, Mayaram K. Sensitivity analysis for oscillators Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 458-463. DOI: 10.1109/Tcad.2008.927731 |
0.342 |
|
| 2007 |
Kurahashi P, Hanumolu PK, Temes GC, Moon UK. Design of low-voltage highly linear switched-R-MOSFET-C filters Ieee Journal of Solid-State Circuits. 42: 1699-1708. DOI: 10.1109/Jssc.2007.900280 |
0.503 |
|
| 2007 |
Carnes J, Vytyaz I, Hanumolu PK, Mayaram K, Moon UK. Design and analysis of noise tolerant ring oscillators using Maneatis delay cells Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 494-497. DOI: 10.1109/ICECS.2007.4511037 |
0.315 |
|
| 2007 |
Wu T, Hanumolu PK, Mayaram K, Moon UK. A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 547-550. DOI: 10.1109/CICC.2007.4405791 |
0.555 |
|
| 2007 |
Hanumolu PK, Wei GY, Moon UK, Mayaram K. Digitally-Enhanced Phase-Locking Circuits Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 361-368. DOI: 10.1109/CICC.2007.4405753 |
0.459 |
|
| 2007 |
Brownlee M, Hanumolu PK, Moon UK. A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 353-356. DOI: 10.1109/CICC.2007.4405751 |
0.655 |
|
| 2007 |
Sasidhar N, Kook YJ, Takeuchi S, Hamashita K, Takasuka K, Hanumolu PK, Moon UK. A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing 2007 Ieee Asian Solid-State Circuits Conference, a-Sscc. 240-243. DOI: 10.1109/ASSCC.2007.4425775 |
0.457 |
|
| 2007 |
Kratyuk V, Hanumolu PK, Moon UK, Mayaram K. Frequency detector for fast frequency lock of digital PLLs Electronics Letters. 43: 13-15. DOI: 10.1049/El:20073292 |
0.44 |
|
| 2006 |
Brownlee M, Hanumolu PK, Mayaram K, Moon UK. A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning Ieee Journal of Solid-State Circuits. 41: 2720-2727. DOI: 10.1109/Jssc.2006.884194 |
0.754 |
|
| 2006 |
Kurahashi P, Hanumolu PK, Ternes G, Moon UK. A 0.6V highly linear switched-R-MOSFET-C filter Proceedings of the Custom Integrated Circuits Conference. 833-836. DOI: 10.1109/CICC.2006.320841 |
0.374 |
|
| 2006 |
Hanumolu PK, Kim MG, Wei GY, Moon UK. A 1.6Gbps digital clock and data recovery circuit Proceedings of the Custom Integrated Circuits Conference. 603-606. DOI: 10.1109/CICC.2006.320829 |
0.527 |
|
| 2006 |
Talebbeydokhti N, Hanumolu PK, Kurahashi P, Moon UK. Constant transconductance bias circuit with an on-chip resistor Proceedings - Ieee International Symposium On Circuits and Systems. 2857-2860. |
0.355 |
|
| 2006 |
Brownlee M, Hanumolu PK, Mayaram K, Moon UK. A 0.5 to 2.5GHz PLL with fully differential supply-regulated tuning Digest of Technical Papers - Ieee International Solid-State Circuits Conference. |
0.71 |
|
| 2006 |
Hanumolu PK, Wei GY, Moon UK. A wide tracking range 0.2-4Gbps clock and data recovery circuit Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 71-72. |
0.535 |
|
| 2006 |
Kim MG, Hanumolu PK, Moon UK. A 10MS/s 11-b 0.19mm2 algorithmic ADC with improved clocking Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 49-50. |
0.38 |
|
| 2006 |
Hanumolu PK, Kratyuk V, Wei GY, Moon UK. A sub-picosecond resolution 0.5-1.5GHz digital-to-phase converter Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 75-76. |
0.507 |
|
| 2006 |
Kratyuk V, Hanumolu PK, Ok K, Mayaram K, Moon UK. A digital PLL with a stochastic time-to-digital converter Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 31-32. |
0.537 |
|
| 2006 |
Ahn G, Hanumolu PK, Kim M, Takeuchi S, Sugimoto T, Hamashita K, Takasuka K, Ternes G, Moon U. A 12b 10MS/s pipelined ADC using reference scaling Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 220-221. |
0.352 |
|
| 2006 |
Kim MG, Ahn GC, Hanumolu PK, Lee SH, Kim SH, You SB, Kim JW, Temes GC, Moon UK. A 0.9V 92dB double-sampled switched-RC ΔΣ audio ADC Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 160-161. |
0.405 |
|
| 2005 |
Hanumolu PK, Wei GY, Moon YK. Equalizers for high-speed serial links International Journal of High Speed Electronics and Systems. 15: 429-458. DOI: 10.1142/S0129156405003259 |
0.428 |
|
| 2005 |
Vemulapalli G, Hanumolu PK, Kook YJ, Moon UK. A 0.8-V accurately tuned linear continuous-time filter Ieee Journal of Solid-State Circuits. 40: 1972-1977. DOI: 10.1109/Jssc.2005.848170 |
0.546 |
|
| 2005 |
Wu T, Hanumolu PK, Moon UK, Mayaram K. An FMDLL based dual-loop frequency synthesizer for 5ghz WLAN applications Proceedings - Ieee International Symposium On Circuits and Systems. 3986-3989. DOI: 10.1109/ISCAS.2005.1465504 |
0.418 |
|
| 2005 |
Kratyuk V, Hanumolu PK, Moon UK, Mayaram K. A low spur fractional-N frequency synthesizer architecture Proceedings - Ieee International Symposium On Circuits and Systems. 2807-2810. DOI: 10.1109/ISCAS.2005.1465210 |
0.381 |
|
| 2004 |
Hanumolu PK, Brownlee M, Mayaram K, Moon UK. Analysis of charge-pump phase-locked loops Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 1665-1674. DOI: 10.1109/Tcsi.2004.834516 |
0.624 |
|
| 2004 |
Vemulapalli G, Hanumolu PK, Moon UK. A 0.8V accurately-tuned continuous-time filter Proceedings of the Custom Integrated Circuits Conference. 45-48. |
0.345 |
|
| 2004 |
Brownlee M, Hanumolu PK, Moon UK, Mayaram K. The effect of power supply noise on ring oscillator phase noise Conference Proceedings - 2nd Annual Ieee Northeast Workshop On Circuits and Systems, Newcas 2004. 225-228. |
0.662 |
|
| 2004 |
Hanumolu PK, Casper B, Mooney R, Wei GY, Moon UK. Jitter in high-speed serial and parallel links Proceedings - Ieee International Symposium On Circuits and Systems. 4: IV-425-IV-428. |
0.304 |
|
| 2003 |
Hanumolu PK, Casper B, Mooney R, Wei GY, Moon UK. Analysis of PLL Clock Jitter in High-Speed Serial Links Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 879-886. DOI: 10.1109/Tcsii.2003.819121 |
0.481 |
|
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