| Year |
Citation |
Score |
| 2020 |
Jung M, Choi W, Kwon M, Srikantaiah S, Yoo J, Kandemir MT. Design of a Host Interface Logic for GC-Free SSDs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1674-1687. DOI: 10.1109/Tcad.2019.2919035 |
0.332 |
|
| 2019 |
Rodriguez G, Kandemir MT, Tourino J. Affine Modeling of Program Traces Ieee Transactions On Computers. 68: 294-300. DOI: 10.1109/Tc.2018.2853747 |
0.435 |
|
| 2019 |
Arslan S, Topcuoglu HR, Kandemir MT, Tosun O. Scheduling opportunities for asymmetrically reliable caches Journal of Parallel and Distributed Computing. 126: 134-151. DOI: 10.1016/J.Jpdc.2019.01.005 |
0.433 |
|
| 2018 |
Shihab MM, Zhang J, Jung M, Kandemir M. ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design Acm Transactions On Architecture and Code Optimization. 15: 17. DOI: 10.1145/3184744 |
0.322 |
|
| 2018 |
Jadidi A, Arjomand M, Kandemir MT, Das CR. Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPs Ieee Transactions On Computers. 67: 1054-1061. DOI: 10.1109/Tc.2018.2796067 |
0.473 |
|
| 2017 |
Arjomand M, Jadidi A, Kandemir MT, Sivasubramaniam A, Das CR. HL-PCM: MLC PCM Main Memory with Accelerated Read Ieee Transactions On Parallel and Distributed Systems. 28: 3188-3200. DOI: 10.1109/Tpds.2017.2705125 |
0.439 |
|
| 2017 |
Arslan S, Topcuoglu HR, Kandemir MT, Tosun O. A selective protection scheme of applications using asymmetrically reliable caches Journal of Systems Architecture. 75: 133-144. DOI: 10.1016/J.Sysarc.2016.12.004 |
0.41 |
|
| 2016 |
Jog A, Kayiran O, Pattnaik A, Kandemir MT, Mutlu O, Iyer R, Das CR. Exploiting core criticality for enhanced GPU performance Sigmetrics/ Performance 2016 - Proceedings of the Sigmetrics/Performance Joint International Conference On Measurement and Modeling of Computer Science. 351-363. DOI: 10.1145/2896377.2901468 |
0.362 |
|
| 2016 |
Rodríguez G, Andión JM, Kandemir MT, Touriño J. Trace-based affine reconstruction of codes Proceedings of the 14th International Symposium On Code Generation and Optimization, Cgo 2016. 139-149. DOI: 10.1145/2854038.2854056 |
0.358 |
|
| 2016 |
Jung M, Choi W, Gao S, Wilson EH, Donofrio D, Shalf J, Kandemir MT. NANDFlashSim: High-fidelity, microarchitecture-aware NAND flash memory simulation Acm Transactions On Storage. 12. DOI: 10.1145/2700310 |
0.478 |
|
| 2016 |
Ozturk O, Orhan U, Ding W, Kandemir M, Yedlapalli P. Cache Hierarchy-Aware Query Mapping on Emerging Multicore Architectures Ieee Transactions On Computers. DOI: 10.1109/Tc.2016.2605682 |
0.41 |
|
| 2016 |
Zhang J, Donofrio D, Shalf J, Kandemir MT, Jung M. NVMMU: A Non-volatile Memory Management Unit for Heterogeneous GPU-SSD Architectures Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 2016: 13-24. DOI: 10.1109/PACT.2015.43 |
0.387 |
|
| 2016 |
Ausavarungnirun R, Ghose S, Kayiran O, Loh GH, Das CR, Kandemir MT, Mutlu O. Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 2016: 25-38. DOI: 10.1109/PACT.2015.38 |
0.356 |
|
| 2016 |
Arjomand M, Jadidi A, Kandemir MT, Sivasubramaniam A, Das C. MLC PCM main memory with accelerated read Ispass 2016 - International Symposium On Performance Analysis of Systems and Software. 143-144. DOI: 10.1109/ISPASS.2016.7482082 |
0.348 |
|
| 2016 |
Kültürsay E, Ebcioğlu K, Küçük G, Kandemir MT. Memory Partitioning in the Limit International Journal of Parallel Programming. 44: 337-380. DOI: 10.1007/S10766-015-0380-7 |
0.448 |
|
| 2016 |
Arslan S, Topcuoglu HR, Kandemir MT, Tosun O. Asymmetrically reliable caches for multicore architectures under performance and energy constraints Cluster Computing. 1-15. DOI: 10.1007/S10586-016-0641-2 |
0.444 |
|
| 2015 |
Jog A, Kayiran O, Kesten T, Pattnaik A, Bolotin E, Chatterjee N, Keckler SW, Kandemir MT, Das CR. Anatomy of GPU memory system for multi-application execution Acm International Conference Proceeding Series. 5: 223-234. DOI: 10.1145/2818950.2818979 |
0.308 |
|
| 2015 |
Cheng HY, Poremba M, Shahidi N, Stalev I, Irwin MJ, Kandemir M, Sampson J, Xie Y. EECache: A comprehensive study on the architectural design for energy-efficient last-level caches in chip multiprocessors Acm Transactions On Architecture and Code Optimization. 12. DOI: 10.1145/2756552 |
0.432 |
|
| 2015 |
Zhao H, Kandemir MT, Irwin MJ. TaPEr: Tackling power emergencies in the dark silicon era by exploiting resource scalability Proceedings of the 12th Acm International Conference On Computing Frontiers, Cf 2015. DOI: 10.1145/2742854.2742868 |
0.309 |
|
| 2015 |
Kayiran O, Nachiappan NC, Jog A, Ausavarungnirun R, Kandemir MT, Loh GH, Mutlu O, Das CR. Managing GPU Concurrency in Heterogeneous Architectures Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2015: 114-126. DOI: 10.1109/MICRO.2014.62 |
0.402 |
|
| 2015 |
Guttman D, Kandemir MT, Arunachalamy M, Calina V. Performance and energy evaluation of data prefetching on intel Xeon Phi Ispass 2015 - Ieee International Symposium On Performance Analysis of Systems and Software. 288-297. DOI: 10.1109/ISPASS.2015.7095814 |
0.379 |
|
| 2015 |
Arslan S, Topcuoglu HR, Kandemir MT, Tosun O. Performance and Energy Efficient Asymmetrically Reliable Caches for Multicore Architectures Proceedings - 2015 Ieee 29th International Parallel and Distributed Processing Symposium Workshops, Ipdpsw 2015. 1025-1032. DOI: 10.1109/IPDPSW.2015.113 |
0.342 |
|
| 2015 |
Guttman D, Kandemir MT, Arunachalam M, Khanna R. Machine learning techniques for improved data prefetching 5th International Conference On Energy Aware Computing Systems and Applications, Iceac 2015. DOI: 10.1109/ICEAC.2015.7352208 |
0.402 |
|
| 2015 |
Kim SJ, Zhang Y, Son SW, Kandemir M, Liao Wk, Thakur R, Choudhary A. IOPro: a parallel I/O profiling and visualization framework for high-performance storage systems Journal of Supercomputing. 71: 840-870. DOI: 10.1007/S11227-014-1329-0 |
0.367 |
|
| 2014 |
Jung M, Wilson EH, Choi W, Shalf J, Aktulga HM, Yang C, Saule E, Catalyurek UV, Kandemir M. Exploring the future of out-of-core computing with compute-local non-volatile memory Scientific Programming. 22: 125-139. DOI: 10.3233/Spr-140384 |
0.443 |
|
| 2014 |
Rodríguez G, Tourinõ J, Kandemir MT. Volatile STT-RAM scratchpad design and data allocation for low energy Acm Transactions On Architecture and Code Optimization. 11. DOI: 10.1145/2669556 |
0.502 |
|
| 2014 |
Nachiappan NC, Yedlapalli P, Soundararajan N, Kandemir MT, Sivasubramaniam A, Das CR. Gemdroid: A framework to evaluate mobile platforms Performance Evaluation Review. 42: 355-366. DOI: 10.1145/2591971.2591973 |
0.356 |
|
| 2014 |
Jog A, Bolotin E, Guz Z, Parker M, Keckler SW, Kandemir MT, Das CR. Application-aware memory system for fair and efficient execution of concurrent GPGPU applications Acm International Conference Proceeding Series. 1-8. DOI: 10.1145/2576779.2576780 |
0.393 |
|
| 2014 |
Jung M, Kandemir MT. Sprinkler: Maximizing resource utilization in many-chip solid state disks Proceedings - International Symposium On High-Performance Computer Architecture. 524-535. DOI: 10.1109/HPCA.2014.6835961 |
0.378 |
|
| 2014 |
Sastry SP, Kultursay E, Shontz SM, Kandemir MT. Improved cache utilization and preconditioner efficiency through use of a space-filling curve mesh element- and vertex-reordering technique Engineering With Computers. 30: 535-547. DOI: 10.1007/S00366-014-0363-0 |
0.355 |
|
| 2013 |
Jog A, Kayiran O, Nachiappan NC, Mishra AK, Kandemir MT, Mutlu O, Iyer R, Das CR. OWL: Cooperative thread array aware scheduling techniques for improving GPGPU performance Acm Sigplan Notices. 48: 395-406. DOI: 10.1145/2499368.2451158 |
0.383 |
|
| 2013 |
Ozturk O, Kandemir M, Chen G. Compiler-directed energy reduction using dynamic voltage scaling and voltage islands for embedded systems Ieee Transactions On Computers. 62: 268-278. DOI: 10.1109/Tc.2011.229 |
0.454 |
|
| 2013 |
Kayiran O, Jog A, Kandemir MT, Das CR. Neither more nor less: Optimizing thread-level parallelism for GPGPUs Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 157-166. DOI: 10.1109/PACT.2013.6618813 |
0.429 |
|
| 2013 |
Swaminathan K, Kultursay E, Saripalli V, Narayanan V, Kandemir MT, Datta S. Steep-slope devices: From dark to dim silicon Ieee Micro. 33: 50-59. DOI: 10.1109/Mm.2013.75 |
0.326 |
|
| 2012 |
Kultursay E, Swaminathan K, Saripalli V, Narayanan V, Kandemir MT, Datta S. Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores Codes+Isss'12 - Proceedings of the 10th Acm International Conference On Hardware/Software-Codesign and System Synthesis, Co-Located With Esweek. 245-254. DOI: 10.1145/2380445.2380487 |
0.341 |
|
| 2012 |
Zhang Y, Liu J, Kultursay E, Kandemir M, Pitsianis N, Sun X. Automatic parallel code generation for NuFFT data translation on multicores Journal of Circuits, Systems and Computers. 21. DOI: 10.1142/S021812661240004X |
0.436 |
|
| 2012 |
Jung M, Wilson EH, Donofrio D, Shalf J, Kandemir MT. NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level Ieee Symposium On Mass Storage Systems and Technologies. DOI: 10.1109/MSST.2012.6232389 |
0.401 |
|
| 2012 |
Oz I, Topcuoglu HR, Kandemir M, Tosun O. Reliability-aware core partitioning in chip multiprocessors Journal of Systems Architecture. 58: 160-176. DOI: 10.1016/J.Sysarc.2012.02.005 |
0.409 |
|
| 2012 |
Oz I, Topcuoglu HR, Kandemir M, Tosun O. Thread vulnerability in parallel applications Journal of Parallel and Distributed Computing. 72: 1171-1185. DOI: 10.1016/J.Jpdc.2012.05.002 |
0.443 |
|
| 2011 |
Demiroz B, Topcuoglu HR, Kandemir M, Tosun O. Particle simulation on the Cell BE architecture Cluster Computing. 14: 419-432. DOI: 10.1007/S10586-011-0169-4 |
0.351 |
|
| 2010 |
Ozturk O, Kandemir M, Irwin MJ. On-chip memory space partitioning for chip multiprocessors using polyhedral algebra Iet Computers and Digital Techniques. 4: 484-498. DOI: 10.1049/Iet-Cdt.2009.0089 |
0.48 |
|
| 2009 |
Ozturk O, Kandemir MT, Son SW, Kolcu I. Shared scratch pad memory space management across applications International Journal of Embedded Systems. 4: 54-65. DOI: 10.1504/Ijes.2009.027240 |
0.437 |
|
| 2009 |
Hu J, Li F, Degalahal V, Kandemir M, Vijaykrishnan N, Irwin MJ. Compiler-assisted soft error detection under performance and energy constraints in embedded systems Acm Transactions in Embedded Computing Systems. 8: 27. DOI: 10.1145/1550987.1550990 |
0.4 |
|
| 2009 |
Unnikrishnan P, Chen G, Kandemir M, Karakoy M, Kolcu I. Reducing memory requirements of resource-constrained applications Acm Transactions On Embedded Computing Systems. 8: 1-37. DOI: 10.1145/1509288.1509289 |
0.51 |
|
| 2009 |
Ozturk O, Kandemir M, Irwin MJ. Using Data Compression for Increasing Memory System Utilization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 901-914. DOI: 10.1109/Tcad.2009.2017430 |
0.508 |
|
| 2009 |
Kim JS, Deng L, Mangalagiri P, Irick K, Sobti K, Kandemir M, Narayanan V, Chakrabarti C, Pitsianis N, Sun X. An automated framework for accelerating numerical algorithms on reconfigurable platforms using algorithmic/architectural optimization Ieee Transactions On Computers. 58: 1654-1667. DOI: 10.1109/Tc.2009.78 |
0.41 |
|
| 2009 |
Mutyam M, Wang F, Krishnan R, Narayanan V, Kandemir M, Xie Y, Irwin MJ. Process-Variation-Aware Adaptive Cache Architecture and Management Ieee Transactions On Computers. 58: 865-877. DOI: 10.1109/Tc.2009.30 |
0.419 |
|
| 2009 |
Ding Y, Kandemir M, Raghavan P, Irwin MJ. Adapting application execution in CMPs using helper threads Journal of Parallel and Distributed Computing. 69: 790-806. DOI: 10.1016/J.Jpdc.2009.04.004 |
0.461 |
|
| 2008 |
Giger G, Kandemir MT, Dzielski J. Graphical Mission Specification and Partitioning for Unmanned Underwater Vehicles Journal of Software. 3: 42-54. DOI: 10.4304/Jsw.3.7.42-54 |
0.34 |
|
| 2008 |
Patrick CM, Son S, Kandemir M. Comparative evaluation of overlap strategies with study of I/O overlap in MPI-IO Operating Systems Review (Acm). 42: 43-49. DOI: 10.1145/1453775.1453784 |
0.339 |
|
| 2008 |
Ozturk O, Kandemir M, Chen G. Access pattern-based code compression for memory-constrained systems Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1391962.1391968 |
0.494 |
|
| 2008 |
Ozturk O, Kandemir M. ILP-based energy minimization techniques for banked memories Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1367045.1367059 |
0.502 |
|
| 2008 |
Gayasen A, Narayanan V, Kandemir M, Rahman A. Designing a 3-D FPGA: Switch box architecture and thermal issues Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 882-893. DOI: 10.1109/Tvlsi.2008.2000456 |
0.329 |
|
| 2008 |
Chen G, Kandemir M. Compiler-Directed Code Restructuring for Improving Performance of MPSoCs Ieee Transactions On Parallel and Distributed Systems. 19: 1201-1214. DOI: 10.1109/Tpds.2007.70760 |
0.53 |
|
| 2008 |
Kadayif I, Zorlubas A, Koyuncu S, Kabal O, Akcicek D, Sahin Y, Kandemir M. Capturing and optimizing the interactions between prefetching and cache line turnoff Microprocessors and Microsystems. 32: 394-404. DOI: 10.1016/J.Micpro.2008.05.003 |
0.435 |
|
| 2007 |
Woo Son S, Chen G, Ozturk O, Kandemir M, Choudhary A. Compiler-Directed Energy Optimization for Parallel Disk Based Systems Ieee Transactions On Parallel and Distributed Systems. 18: 1241-1257. DOI: 10.1109/Tpds.2007.1056 |
0.428 |
|
| 2007 |
Topcuoglu HR, Demiroz B, Kandemir M. Solving the Register Allocation Problem for Embedded Systems Using a Hybrid Evolutionary Algorithm Ieee Transactions On Evolutionary Computation. 11: 620-634. DOI: 10.1109/Tevc.2007.892766 |
0.431 |
|
| 2007 |
Kadayif I, Nath P, Kandemir M, Sivasubramaniam A. Reducing data TLB power via compiler-directed address generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 312-324. DOI: 10.1109/Tcad.2006.882599 |
0.496 |
|
| 2007 |
Hu J, Vijaykrishnan N, Irwin MJ, Kandemir M. Optimising power efficiency in trace cache fetch unit Iet Computers and Digital Techniques. 1: 334-348. DOI: 10.1049/Iet-Cdt:20060170 |
0.413 |
|
| 2007 |
Son SW, Malkowski K, Chen G, Kandemir M, Raghavan P. Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling Journal of Supercomputing. 41: 179-213. DOI: 10.1007/S11227-007-0113-9 |
0.406 |
|
| 2006 |
Memik G, Kandemir MT, Liao WK, Choudhary A. Multicollective I/O: A technique for exploiting inter-file access patterns Acm Transactions On Storage. 2: 349-369. DOI: 10.1145/1168910.1168915 |
0.415 |
|
| 2006 |
Kandemir MT. Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality Acm Transactions On Design Automation of Electronic Systems. 11: 410-441. DOI: 10.1145/1142155.1142163 |
0.521 |
|
| 2006 |
Chen G, Kandemir M, Irwin MJ, Ramanujam J. Reducing code size through address register assignment Acm Transactions On Embedded Computing Systems (Tecs). 5: 225-258. DOI: 10.1145/1132357.1132365 |
0.473 |
|
| 2006 |
Zhang W, Tsai Y, Duarte D, Vijaykrishnan N, Kandemir M, Irwin MJ. Reducing dynamic and leakage energy in VLIW architectures Acm Transactions On Embedded Computing Systems (Tecs). 5: 1-28. DOI: 10.1145/1132357.1132358 |
0.429 |
|
| 2006 |
Kandemir M, Ramanujam J, Sezer U. Improving the energy behavior of block buffering using compiler optimizations Acm Transactions On Design Automation of Electronic Systems. 11: 228-250. DOI: 10.1145/1124713.1124727 |
0.477 |
|
| 2006 |
Luz VDL, Kandemir M, Kolcu I. Reducing memory energy consumption of embedded applications that process dynamically allocated data Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1855-1860. DOI: 10.1109/Tcad.2005.859521 |
0.471 |
|
| 2006 |
Vilayannur M, Sivasubramaniam A, Kandemir M, Thakur R, Ross R. Discretionary caching for I/O on clusters Cluster Computing. 9: 29-44. DOI: 10.1007/S10586-006-4895-Y |
0.403 |
|
| 2005 |
Lattanzi E, Gayasen A, Kandemir MT, Vijaykrishnan N, Benini L, Bogliolo A. Improving Java performance using dynamic method migration on FPGAs International Journal of Embedded Systems. 1: 228-236. DOI: 10.1504/Ijes.2005.009952 |
0.425 |
|
| 2005 |
Swankoski EJ, Vijaykrishnan N, Brooks R, Kandemir M, Irwin M. Symmetric encryption in reconfigurable and custom hardware International Journal of Embedded Systems. 1: 205. DOI: 10.1504/Ijes.2005.009950 |
0.393 |
|
| 2005 |
Hu J, Kandemir M, Vijaykrishnan N, Irwin MJ. Analyzing data reuse for cache reconfiguration Acm Transactions in Embedded Computing Systems. 4: 851-876. DOI: 10.1145/1113830.1113836 |
0.485 |
|
| 2005 |
Kadayif I, Kandemir M, Chen G, Vijaykrishnan N, Irwin MJ, Sivasubramaniam A. Compiler-directed high-level energy estimation and optimization Acm Transactions in Embedded Computing Systems. 4: 819-850. DOI: 10.1145/1113830.1113835 |
0.461 |
|
| 2005 |
Zhang W, Kandemir M, Karakoy M, Chen G. Reducing data cache leakage energy using a compiler-based approach Acm Transactions On Embedded Computing Systems. 4: 652-678. DOI: 10.1145/1086519.1086529 |
0.534 |
|
| 2005 |
Kadayif I, Kandemir M. Data space-oriented tiling for enhancing locality Acm Transactions in Embedded Computing Systems. 4: 388-414. DOI: 10.1145/1067915.1067922 |
0.476 |
|
| 2005 |
Kadayif I, Sivasubramaniam A, Kandemir M, Kandiraju G, Chen G. Optimizing instruction TLB energy using software and hardware techniques Acm Transactions On Design Automation of Electronic Systems. 10: 229-257. DOI: 10.1145/1059876.1059879 |
0.393 |
|
| 2005 |
Kandemir M, Irwin M, Chen G, Kolcu I. Compiler-guided leakage optimization for banked scratch-pad memories Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1136-1146. DOI: 10.1109/Tvlsi.2005.859478 |
0.508 |
|
| 2005 |
Degalahal V, Li L, Narayanan V, Kandemir M, Irwin MJ. Soft errors issues in low-power caches Ieee Transactions On Very Large Scale Integration Systems. 13: 1157-1166. DOI: 10.1109/Tvlsi.2005.859474 |
0.38 |
|
| 2005 |
Kadayif I, Kandemir M, Chen G, Ozturk O, Karakoy M, Sezer U. Optimizing array-intensive applications for on-chip multiprocessors Ieee Transactions On Parallel and Distributed Systems. 16: 396-411. DOI: 10.1109/Tpds.2005.57 |
0.503 |
|
| 2005 |
Kim EJ, Link GM, Yum KH, Vijaykrishnan N, Kandemir M, Irwin MJ, Das CR. A holistic approach to designing energy-efficient cluster interconnects Ieee Transactions On Computers. 54: 660-671. DOI: 10.1109/Tc.2005.86 |
0.426 |
|
| 2005 |
Kandemir MT. Improving whole-program locality using intra-procedural and inter-procedural transformations Journal of Parallel and Distributed Computing. 65: 564-582. DOI: 10.1016/J.Jpdc.2004.12.004 |
0.452 |
|
| 2005 |
Chiu SC, Liao W, Choudhary AN, Kandemir MT. Erratum: Processor-embedded distributed smart disks for I/O-intensive workloads: Architectures, performance models and evaluation (Journal of Parallel and Distributed Computing (2004) 64 (427-446) doi: 10.1016/j.jpdc.2004.01.004) Journal of Parallel and Distributed Computing. 65. DOI: 10.1016/J.Jpdc.2004.10.005 |
0.34 |
|
| 2005 |
Kadayif I, Kandemir M, Vijaykrishnan N, Irwin MJ. An integer linear programming-based tool for wireless sensor networks Journal of Parallel and Distributed Computing. 65: 247-260. DOI: 10.1016/J.Jpdc.2004.04.004 |
0.351 |
|
| 2005 |
Kim S, Vijaykrishnan N, Kandemir M, Irwin MJ. Optimizing leakage energy consumption in cache bitlines Design Automation For Embedded Systems. 9: 5-18. DOI: 10.1007/S10617-005-5345-4 |
0.373 |
|
| 2005 |
Memik G, Kandemir MT, Mallik A. Load elimination for low-power embedded processors Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 282-285. |
0.321 |
|
| 2004 |
Zhang W, Hu JS, Degalahal V, Kandemir M, Vijaykrishnan N, Irwin MJ. Reducing instruction cache energy consumption using a compiler-based strategy Acm Transactions On Architecture and Code Optimization. 1: 3-33. DOI: 10.1145/980152.980154 |
0.472 |
|
| 2004 |
Kadayif I, Kandemir M. Quasidynamic layout optimizations for improving data locality Ieee Transactions On Parallel and Distributed Systems. 15: 996-1011. DOI: 10.1109/Tpds.2004.70 |
0.487 |
|
| 2004 |
Chen G, Kang B, Kandemir M, Vijaykrishnan N, Irwin M, Chandramouli R. Studying energy trade offs in offloading computation/compilation in Java-enabled mobile devices Ieee Transactions On Parallel and Distributed Systems. 15: 795-809. DOI: 10.1109/Tpds.2004.47 |
0.429 |
|
| 2004 |
De La Luz V, Kadayif I, Kandemir M, Sezer U. Access pattern restructuring for memory energy Ieee Transactions On Parallel and Distributed Systems. 15: 289-303. DOI: 10.1109/Tpds.2004.1271179 |
0.493 |
|
| 2004 |
Kandemir M, Ramanujam J, Irwin MJ, Vijaykrishnan N, Kadayif I, Parikh A. A compiler-based approach for dynamically managing scratch-pad memories in embedded systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 243-260. DOI: 10.1109/Tcad.2003.822123 |
0.496 |
|
| 2004 |
Luz VDL, Kandemir M. Array regrouping and its use in compiling data-intensive, embedded applications Ieee Transactions On Computers. 53: 1-19. DOI: 10.1109/Tc.2004.1255787 |
0.536 |
|
| 2004 |
Chiu SC, Liao Wk, Choudhary AN, Kandemir MT. Processor-embedded distributed smart disks for I/O-intensive workloads: Architectures, performance models and evaluation Journal of Parallel and Distributed Computing. 64: 427-446. DOI: 10.1016/J.Jpdc.2004.01.004 |
0.444 |
|
| 2004 |
Kandemir MT. Exploiting memory bank locality in multiprocessor SoC architectures Proceedings - International Parallel and Distributed Processing Symposium, Ipdps 2004 (Abstracts and Cd-Rom). 18: 1307-1316. |
0.419 |
|
| 2003 |
Kim S, Vijaykrishnan N, Kandemir M, Sivasubramaniam A, Irwin MJ. Partitioned instruction cache architecture for energy efficiency Acm Transactions in Embedded Computing Systems. 2: 163-185. DOI: 10.1145/643470.643473 |
0.498 |
|
| 2003 |
Shen X, Liao WK, Choudhary A, Memik G, Kandemir M. A high-performance application data environment for large-scale scientific computations Ieee Transactions On Parallel and Distributed Systems. 14: 1262-1274. DOI: 10.1109/Tpds.2003.1255638 |
0.44 |
|
| 2003 |
Kandemir M, Choudhary A, Ramanujam J, Banerjee P. Reducing false sharing and improving spatial locality in a unified compilation framework Ieee Transactions On Parallel and Distributed Systems. 14: 337-354. DOI: 10.1109/Tpds.2003.1195407 |
0.462 |
|
| 2003 |
Vijaykrishnan N, Kandemir M, Irwin MJ, Kim HS, Ye W, Duarte D. Evaluating integrated hardware-software optimizations using a unified energy estimation framework Ieee Transactions On Computers. 52: 59-76. DOI: 10.1109/Tc.2003.1159754 |
0.429 |
|
| 2003 |
Gurumurthi S, Sivasubramaniam A, Kandemir M, Franke H. Reducing Disk Power Consumption in Servers with DRPM Computer. 36: 59-66. DOI: 10.1109/Mc.2003.1250884 |
0.354 |
|
| 2002 |
Chen G, Shetty R, Kandemir M, Vijaykrishnan N, Irwin MJ, Wolczko M. Tuning garbage collection for reducing memory system energy in an embedded java environment Acm Transactions On Embedded Computing Systems (Tecs). 1: 27-55. DOI: 10.1145/581888.581892 |
0.494 |
|
| 2002 |
Chen G, Kandemir M, Vijaykrishnan N, Irwin MJ, Wolf W. Using memory compression for energy reduction in an embedded java system Journal of Circuits, Systems and Computers. 11: 537-555. DOI: 10.1142/S0218126602000604 |
0.48 |
|
| 2002 |
Kandaswamy MA, Kandemir M, Choudhary A, Bernholdt D. Erratum: An experimental evaluation of I/O optimizations on different applications (IEEE Transactions on Parallel and Distributed Systems) Ieee Transactions On Parallel and Distributed Systems. 13: 1303-1319. DOI: 10.1109/Tpds.2002.1158267 |
0.375 |
|
| 2002 |
Kandaswamy MA, Kandemir M, Choudhary A, Bernholdt D. An experimental evaluation of I/O optimizations on different applications Ieee Transactions On Parallel and Distributed Systems. 13: 1303-1319. DOI: 10.1109/Tpds.2002.1019861 |
0.443 |
|
| 2002 |
Kadayif I, Kandemir MT. Instruction compression and encoding for low-power systems Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 301-305. DOI: 10.1109/ASIC.2002.1158075 |
0.365 |
|
| 2002 |
Kandemir M, Choudhary A, Ramanujam J. An I/O-conscious tiling strategy for disk-resident data sets Journal of Supercomputing. 21: 257-284. DOI: 10.1023/A:1014156327748 |
0.397 |
|
| 2002 |
Kandemir MT. Compiler-directed optimizations for improving the performance of I/O-intensive applications International Journal of Parallel and Distributed Systems and Networks. 5: 52-65. |
0.412 |
|
| 2002 |
Zambreno J, Kandemir MT, Choudhary A. Enhancing compiler techniques for memory energy optimizations Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2491: 364-381. |
0.391 |
|
| 2001 |
Esakkimuthu G, Kim HS, Kandemir MT, Vijaykrishnan N, Irwin MJ. Investigating Memory System Energy Behavior Using Software and Hardware Optimizations Vlsi Design. 2001: 151-165. DOI: 10.1155/2001/70310 |
0.492 |
|
| 2001 |
Kandemir M, Banerjee P, Choudhary A, Ramanujam J, Ayguadé E. Static and dynamic locality optimizations using integer linear programming Ieee Transactions On Parallel and Distributed Systems. 12: 922-941. DOI: 10.1109/Tpds.2001.1184186 |
0.488 |
|
| 2001 |
Kandemir M, Ramanujam J, Choudhary A, Banerjee P. A layout-conscious iteration space transformation technique Ieee Transactions On Computers. 50: 1321-1336. DOI: 10.1109/Tc.2001.970571 |
0.471 |
|
| 2001 |
Kandemir M, Vijaykrishnan N, Irwin MJ, Ye W. Influence of compiler optimizations on system power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 801-804. DOI: 10.1109/92.974893 |
0.466 |
|
| 2001 |
Kandemir M. Compiler-directed Collective-I/O Ieee Transactions On Parallel and Distributed Systems. 12: 1318-1331. DOI: 10.1109/71.970566 |
0.374 |
|
| 2001 |
Delaluz V, Kandemir M, Vijaykrishnan N, Sivasubramaniam A, Irwin MJ. Hardware and software techniques for controlling DRAM power modes Ieee Transactions On Computers. 50: 1154-1173. DOI: 10.1109/12.966492 |
0.436 |
|
| 2001 |
Kandemir MT. Array unification: A locality optimization technique Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2027: 259-273. DOI: 10.1007/3-540-45306-7_18 |
0.37 |
|
| 2001 |
Memik G, Kandemir MT, Choudhary A. Design and evaluation of a smart disk clusters for DSS commercial workloads Journal of Parallel and Distributed Computing. 61: 1633-1664. DOI: 10.1006/Jpdc.2001.1743 |
0.401 |
|
| 2001 |
Kandemir MT. A compiler technique for improving whole-program locality Conference Record of the Annual Acm Symposium On Principles of Programming Languages. 179-192. |
0.347 |
|
| 2000 |
Memik G, Kandemir MT, Choudhary A. Design and evaluation of smart disk architecture for DSS commercial workloads Proceedings of the International Conference On Parallel Processing. 2000: 335-342. DOI: 10.1109/ICPP.2000.876149 |
0.311 |
|
| 2000 |
Kandemir M, Choudhary A, Banerjee P, Ramanujam J, Shenoy N. Minimizing data and synchronization costs in one-way communication Ieee Transactions On Parallel and Distributed Systems. 11: 1232-1251. DOI: 10.1109/71.895791 |
0.352 |
|
| 2000 |
Kandemir M, Choudhary A, Ramanujam J, Kandaswamy MA. A unified framework for optimizing locality, parallelism, and communication in out-of-core computations Ieee Transactions On Parallel and Distributed Systems. 11: 648-668. DOI: 10.1109/71.877759 |
0.513 |
|
| 2000 |
Kandemir M, Ramanujam J. Data relation vectors: a new abstraction for data optimizations Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 227-236. DOI: 10.1109/12.947000 |
0.447 |
|
| 2000 |
Choudhary A, Kandemir M, No J, Memik G, Shen X, Liao W, Nagesh H, More S, Taylor V, Thakur R, Stevens R. Data management for large-scale scientific computations in high performance distributed systems Cluster Computing. 3: 45-60. DOI: 10.1023/A:1019063700437 |
0.429 |
|
| 2000 |
Kandemir MT. A collective I/O scheme based on compiler analysis Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1915: 1-15. DOI: 10.1007/3-540-40889-4_1 |
0.364 |
|
| 1999 |
Kandemir M, Banerjee P, Choudhary A, Ramanujam J, Shenoy N. A global communication optimization technique based on data-flow analysis and linear algebra Acm Transactions On Programming Languages and Systems. 21: 1251-1297. DOI: 10.1145/330643.330647 |
0.408 |
|
| 1999 |
Kandemir M, Choudhary A, Shenoy N, Banerjee P, Ramanujam J. A linear algebra framework for automatic determination of optimal data layouts Ieee Transactions On Parallel and Distributed Systems. 10: 115-135. DOI: 10.1109/71.752779 |
0.419 |
|
| 1999 |
Kandemir M, Ramanujam J, Choudhary A. Improving cache locality by a combination of loop and data transformations Ieee Transactions On Computers. 48: 159-167. DOI: 10.1109/12.752657 |
0.44 |
|
| 1999 |
Kandemir M, Choudhary A, Ramanujam J, Banerjee P. A Matrix-Based Approach to Global Locality Optimization Journal of Parallel and Distributed Computing. 58: 190-235. DOI: 10.1006/Jpdc.1999.1552 |
0.419 |
|
| 1998 |
Kandemir M, Choudhary A, Ramanujam J. Improving locality in out-of-core computations using data layout transformations Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1511: 359-366. DOI: 10.1007/3-540-49530-4_27 |
0.459 |
|
| 1997 |
Adve SV, Burger D, Eigenmann R, Rawsthorne A, Smith MD, Gebotys CH, Kandemir MT, Lilja DJ, Choudhary AN, Fang JZ, Yew PC. Changing interaction of compiler and architecture Computer. 30: 51-58. DOI: 10.1109/2.642815 |
0.369 |
|
| 1997 |
Kandemir M, Ramanujam J, Choudhary A. Compiler algorithms for optimizing locality and parallelism on shared and distributed memory machines Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 236-245. DOI: 10.1006/Jpdc.2000.1639 |
0.514 |
|
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