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N Vijaykrishnan - Publications

Affiliations: 
Pennsylvania State University, State College, PA, United States 
Area:
Computer Science
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93 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2011 Wang F, Chen Y, Nicopoulos C, Wu X, Xie Y, Vijaykrishnan N. Variation-Aware Task and Communication Mapping for MPSoC Architecture Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 295-307. DOI: 10.1109/Tcad.2010.2077830  0.343
2011 Mishra AK, Yanamandra A, Das R, Eachempati S, Iyer R, Vijaykrishnan N, Das CR. RAFT: A router architecture with frequency tuning for on-chip networks Journal of Parallel and Distributed Computing. 71: 625-640. DOI: 10.1016/J.Jpdc.2010.09.005  0.41
2009 Hu J, Li F, Degalahal V, Kandemir M, Vijaykrishnan N, Irwin MJ. Compiler-assisted soft error detection under performance and energy constraints in embedded systems Acm Transactions in Embedded Computing Systems. 8: 27. DOI: 10.1145/1550987.1550990  0.418
2009 Irick KM, Debole M, Park S, Al Maashri A, Kestur S, Yu CL, Vijaykrishnan N. A scalable multi-FPGA framework for real-time digital signal processing Proceedings of Spie - the International Society For Optical Engineering. 7444. DOI: 10.1117/12.834177  0.395
2008 Yang S, Wang W, Lu T, Wolf W, Vijaykrishnan N, Xie Y. Case Study of Reliability-Aware and Low-Power Design Ieee Transactions On Very Large Scale Integration Systems. 16: 861-873. DOI: 10.1109/Tvlsi.2008.2000460  0.332
2008 Tsai YF, Wang F, Xie Y, Vijaykrishnan N, Irwin MJ. Design space exploration for 3-D Cache Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 444-455. DOI: 10.1109/Tvlsi.2007.915429  0.361
2008 Srinivasan S, Li L, Ruggiero M, Angiolini F, Vijaykrishnan N, Benini L. Exploring architectural solutions for energy optimisations in bus-based system-on-chip Iet Computers and Digital Techniques. 2: 347-354. DOI: 10.1049/iet-cdt:20070063  0.364
2007 Gayasen A, Srinivasan S, Vijaykrishnan N, Kandemir M. Design of power-aware FPGA fabrics International Journal of Embedded Systems. 3: 52-64. DOI: 10.1504/IJES.2007.016033  0.318
2007 Li T, John LK, Sivasubramaniam A, Vijaykrishnan N, Rubio J. OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems Ieee Transactions On Computers. 56: 2-17. DOI: 10.1109/Tc.2007.16  0.316
2007 Hu J, Vijaykrishnan N, Irwin MJ, Kandemir M. Optimising power efficiency in trace cache fetch unit Iet Computers and Digital Techniques. 1: 334-348. DOI: 10.1049/Iet-Cdt:20060170  0.319
2007 Kim S, Vijaykrishnan N, Irwin MJ. Reducing non-deterministic loads in low-power caches via early cache set resolution Microprocessors and Microsystems. 31: 293-301. DOI: 10.1016/J.Micpro.2006.10.002  0.3
2006 Zhang W, Tsai Y, Duarte D, Vijaykrishnan N, Kandemir M, Irwin MJ. Reducing dynamic and leakage energy in VLIW architectures Acm Transactions On Embedded Computing Systems (Tecs). 5: 1-28. DOI: 10.1145/1132357.1132358  0.476
2006 Lee J, Vijaykrishnan N, Irwin MJ, Chandramouli R. Block-based frequency scalable technique for efficient hierarchical coding Ieee Transactions On Signal Processing. 54: 2559-2566. DOI: 10.1109/Tsp.2006.874806  0.332
2006 Lee J, Vijaykrishnan N, Irwin MJ. Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties Ieee Transactions On Circuits and Systems For Video Technology. 16: 655-662. DOI: 10.1109/Tcsvt.2006.873155  0.312
2006 Lee J, Vijaykrishnan N, Irwin MJ, Wolf W. An efficient architecture for motion estimation and compensation in the transform domain Ieee Transactions On Circuits and Systems For Video Technology. 16: 191-201. DOI: 10.1109/Tcsvt.2005.857780  0.313
2006 Park D, Nicopoulos C, Kim J, Vijaykrishnan N, Das CR. A distributed multi-point network interface for low-latency, deadlock-free on-chip interconnects 2006 1st International Conference On Nano-Networks and Workshops, Nano-Net. DOI: 10.1109/NANONET.2006.346214  0.308
2006 Mutyam M, Eze M, Vijaykrishnan N, Xie Y. Delay and energy efficient data transmission for on-chip buses Proceedings - Ieee Computer Society Annual Symposium On Emerging Vlsi Technologies and Architectures 2006. 2006: 355-360. DOI: 10.1109/ISVLSI.2006.33  0.374
2005 Hu J, Kandemir M, Vijaykrishnan N, Irwin MJ. Analyzing data reuse for cache reconfiguration Acm Transactions in Embedded Computing Systems. 4: 851-876. DOI: 10.1145/1113830.1113836  0.47
2005 Kadayif I, Kandemir M, Chen G, Vijaykrishnan N, Irwin MJ, Sivasubramaniam A. Compiler-directed high-level energy estimation and optimization Acm Transactions in Embedded Computing Systems. 4: 819-850. DOI: 10.1145/1113830.1113835  0.476
2005 Kim EJ, Link GM, Yum KH, Vijaykrishnan N, Kandemir M, Irwin MJ, Das CR. A holistic approach to designing energy-efficient cluster interconnects Ieee Transactions On Computers. 54: 660-671. DOI: 10.1109/Tc.2005.86  0.473
2005 Saputra H, Ozturk O, Vijaykrishnan N, Kandemir M, Brooks R. A data-driven approach for embedded security Proceedings - Ieee Computer Society Annual Symposium On Vlsi - New Frontiers in Vlsi. 104-109. DOI: 10.1109/ISVLSI.2005.4  0.661
2005 Srinivasan S, Li L, Vijaykrishnan N. Simultaneous partitioning and frequency assignment for on-chip bus architectures Proceedings -Design, Automation and Test in Europe, Date '05. 218-223. DOI: 10.1109/DATE.2005.269  0.329
2005 Yang S, Wolf W, Vijaykrishnan N, Serpanos DN, Xie Y. Power attack resistant cryptosystem design: A dynamic voltage and frequency switching approach Proceedings -Design, Automation and Test in Europe, Date '05. 2005: 64-69. DOI: 10.1109/DATE.2005.241  0.321
2005 Kim J, Park D, Nicopoulos C, Vijaykrishnan N, Das CR. Design and analysis of an NoC architecture from performance, reliability and energy perspective 2005 Symposium On Architectures For Networking and Communications Systems, Ancs 2005. 173-182. DOI: 10.1109/ANCS.2005.4675277  0.354
2005 Kadayif I, Kandemir M, Vijaykrishnan N, Irwin MJ. An integer linear programming-based tool for wireless sensor networks Journal of Parallel and Distributed Computing. 65: 247-260. DOI: 10.1016/J.Jpdc.2004.04.004  0.402
2005 Irwin MJ, Benini L, Vijaykrishnan N, Kandemir M. Techniques for Designing Energy-Aware MPSoCs Multiprocessor Systems-On-Chips. 21-47. DOI: 10.1016/B978-012385251-9/50016-5  0.385
2005 Kim S, Vijaykrishnan N, Kandemir M, Irwin MJ. Optimizing leakage energy consumption in cache bitlines Design Automation For Embedded Systems. 9: 5-18. DOI: 10.1007/S10617-005-5345-4  0.322
2005 Kim J, Park D, Theocharides T, Vijaykrishnan N, Das CR. A low latency router supporting adaptivity for on-chip interconnects Proceedings - Design Automation Conference. 559-564.  0.365
2005 Srinivasan S, Angiolini F, Ruggiero M, Benini L, Vijaykrishnan N. Simultaneous memory and bus partitioning for SoC architectures Proceedings - Ieee International Soc Conference. 125-128.  0.389
2004 Zhang W, Hu JS, Degalahal V, Kandemir M, Vijaykrishnan N, Irwin MJ. Reducing instruction cache energy consumption using a compiler-based strategy Acm Transactions On Architecture and Code Optimization. 1: 3-33. DOI: 10.1145/980152.980154  0.458
2004 Tsai YF, Duarte DE, Vijaykrishnan N, Irwin MJ. Characterization and modeling of run-time techniques for leakage power reduction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1221-1232. DOI: 10.1109/Tvlsi.2004.836315  0.389
2004 Chen G, Kang B, Kandemir M, Vijaykrishnan N, Irwin M, Chandramouli R. Studying energy trade offs in offloading computation/compilation in Java-enabled mobile devices Ieee Transactions On Parallel and Distributed Systems. 15: 795-809. DOI: 10.1109/Tpds.2004.47  0.444
2004 Kandemir M, Ramanujam J, Irwin MJ, Vijaykrishnan N, Kadayif I, Parikh A. A compiler-based approach for dynamically managing scratch-pad memories in embedded systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 243-260. DOI: 10.1109/Tcad.2003.822123  0.369
2004 Li L, Degalahal V, Vijaykrishnan N, Kandemir M, Irwin MJ. Soft error and energy consumption interactions: A data cache perspective Proceedings of the 2004 International Symposium On Lower Power Electronics and Design, Islped'04. 132-137. DOI: 10.1109/LPE.2004.240852  0.342
2004 Hu JS, Vijaykrishnan N, Kim S, Kandemir M, Irwin MJ. Scheduling reusable instructions for power reduction Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 148-153. DOI: 10.1109/DATE.2004.1268841  0.309
2004 Kim S, Tomar S, Vijaykrishnan N, Kandemir M, Irwin MJ. Energy-efficient Java execution using local memory and object co-location Iee Proceedings: Computers and Digital Techniques. 151: 33-42. DOI: 10.1049/ip-cdt:20040186  0.366
2004 Juran J, Hurson AR, Vijaykrishnan N, Kim S. Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues Wireless Networks. 10: 183-195. DOI: 10.1023/B:Wine.0000013082.03518.2E  0.404
2004 Parikh A, Kim S, Kandemir M, Vijaykrishnan N, Irwin MJ. Instruction Scheduling for Low Power Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 37: 129-149. DOI: 10.1023/B:VLSI.0000017007.28247.f6  0.382
2004 DeRenzo M, Irwin MJ, Vijaykrishnan N. Designing leakage aware multipliers Proceedings of the Ieee International Conference On Vlsi Design. 17: 654-657.  0.329
2003 Chen G, Vijaykrishnan N, Kandemir M, Irwin MJ, Wolczko M. Tracking Object Life Cycle for Leakage Energy Optimization Hardware/Software Codesign - Proceedings of the International Workshop. 213-218. DOI: 10.1145/944700.944701  0.322
2003 Kim S, Vijaykrishnan N, Kandemir M, Sivasubramaniam A, Irwin MJ. Partitioned instruction cache architecture for energy efficiency Acm Transactions in Embedded Computing Systems. 2: 163-185. DOI: 10.1145/643470.643473  0.496
2003 Vijaykrishnan N, Kandemir M, Irwin MJ, Kim HS, Ye W, Duarte D. Evaluating integrated hardware-software optimizations using a unified energy estimation framework Ieee Transactions On Computers. 52: 59-76. DOI: 10.1109/Tc.2003.1159754  0.451
2003 Saputra H, Vijaykrishnan N, Kandemir M, Brooks R, Irwin MJ. Exploiting value locality for secure-energy aware communication Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2003: 116-121. DOI: 10.1109/SIPS.2003.1235654  0.651
2003 Duarte DE, Vijaykrishnan N, Irwin MJ. A clock power model to evaluate impact of architectural and technology optimizations - A summary Ieee Circuits and Systems Magazine. 3: 36-39. DOI: 10.1109/Mcas.2003.1263398  0.404
2003 Hu JS, Vijaykrishnan N, Irwin MJ, Kandemir M. Using dynamic branch behavior for power-efficient instruction fetch Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2003: 127-132. DOI: 10.1109/ISVLSI.2003.1183363  0.302
2003 Zhang W, Kandemir M, Vijaykrishnan N, Irwin MJ, De V. Compiler support for reducing leakage energy consumption Proceedings -Design, Automation and Test in Europe, Date. 1146-1147. DOI: 10.1109/DATE.2003.1253774  0.332
2003 Saputra H, Vijaykrishnan N, Kandemir M, Irwin MJ, Brooks R. Masking the energy behaviour of encryption algorithms Iee Proceedings: Computers and Digital Techniques. 150: 274-284. DOI: 10.1049/ip-cdt:20030832  0.687
2003 Li L, Vijaykrishnan N, Kandemir M, Irwin MJ. Adaptive error protection for energy efficiency Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 2-7.  0.307
2003 Kim HS, Vijaykrishnan N, Kandemir M, Irwin MJ. Adapting instruction level parallelism for optimizing leakage in VLIW architectures Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes). 275-283.  0.359
2003 Kim S, Vijaykrishnan N, Irwin MJ, John LK. On Load Latency in Low-Power Caches Proceedings of the International Symposium On Low Power Electronics and Design. 258-261.  0.318
2003 Hu JS, Nadgir A, Vijaykrishnan N, Irwin MJ, Kandemir M. Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management Proceedings of the International Symposium On Low Power Electronics and Design. 402-407.  0.368
2003 Delaluz V, Kandemir M, Sivasubramaniam A, Irwin MJ, Vijaykrishnan N. Reducing dTLB energy through dynamic resizing Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 358-363.  0.397
2003 Li L, Vijaykrishnan N, Kandemir M, Irwin MJ, Kadayif I. CCC: Crossbar connected caches for reducing energy consumption of on-chip multiprocessors Proceedings - Euromicro Symposium On Digital System Design, Dsd 2003. 41-48.  0.389
2002 Chen G, Shetty R, Kandemir M, Vijaykrishnan N, Irwin MJ, Wolczko M. Tuning garbage collection for reducing memory system energy in an embedded java environment Acm Transactions On Embedded Computing Systems (Tecs). 1: 27-55. DOI: 10.1145/581888.581892  0.447
2002 Chen G, Kandemir M, Vijaykrishnan N, Irwin MJ, Wolf W. Using memory compression for energy reduction in an embedded java system Journal of Circuits, Systems and Computers. 11: 537-555. DOI: 10.1142/S0218126602000604  0.347
2002 Duarte DE, Vijaykrishnan N, Irwin MJ. A clock power model to evaluate impact of architectural and technology optimizations Ieee Transactions On Very Large Scale Integration Systems. 10: 844-855. DOI: 10.1109/Tvlsi.2002.808433  0.405
2002 Kadayif I, Kandemir M, Vijaykrishnan N, Irwin MJ. Hardware-software co-adaptation for data-intensive embedded applications Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2002: 20-25. DOI: 10.1109/ISVLSI.2002.1016868  0.369
2002 Sivasubramaniam A, Kandemir M, Vijaykrishnan N, Irwin MJ. Designing energy-efficient software Proceedings - International Parallel and Distributed Processing Symposium, Ipdps 2002. 176-183. DOI: 10.1109/IPDPS.2002.1016580  0.346
2002 Chen G, Shetty R, Kandemir M, Vijaykrishnan N, Irwin MJ, Wolczko M. Tuning garbage collection in an embedded Java environment Proceedings - International Symposium On High-Performance Computer Architecture. 2002: 92-103. DOI: 10.1109/HPCA.2002.995701  0.338
2002 Kadayif I, Kandemir M, Vijaykrishnan N, Irwin MJ, Sivasubramaniam A. EAC: A compiler framework for high-level energy estimation and optimization Proceedings -Design, Automation and Test in Europe, Date. 436-442. DOI: 10.1109/DATE.2002.998310  0.327
2002 Zhao J, Chandramouli R, Vijaykrishnan N, Irwirn MJ, Kang B, Somasundaram S. Influence of MPEG-4 parameters on system energy Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 137-142. DOI: 10.1109/ASIC.2002.1158045  0.341
2002 Kim S, Vijaykrishnan N, Kandemir M, Irwin MJ. Predictive precharging for bitline leakage energy reduction Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 36-40. DOI: 10.1109/ASIC.2002.1158027  0.318
2002 Hu JS, Kandemir M, Vijaykrishnan N, Irwin MJ, Saputra H, Zhang W. Compiler-directed cache polymorphism Joint Conference On Languages, Compilers and Tools For Embedded Systems and Software and Compilers For Embedded Systems. 165-174.  0.662
2002 Duarte D, Vijaykrishnan N, Irwin MJ, Kim HS, McFarland G. Impact of scaling on the effectiveness of dynamic power reduction schemes Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 382-387.  0.328
2002 Delaluz V, Sivasubramaniam A, Kandemir M, Vijaykrishnan N, Irwin MJ. Scheduler-based DRAM energy management Proceedings - Design Automation Conference. 697-702.  0.364
2002 Chen G, Kandemir M, Vijaykrishnan N, Irwin MJ, Wolf W. Energy savings through compression in embedded Java environments Hardware/Software Codesign - Proceedings of the International Workshop. 163-168.  0.346
2001 Kirubanandan N, Sivasubramaniam A, Vijaykrishnan N, Kandemir M, Irwin MJ. Memory energy characterization and optimization for the SPEC2000 benchmarks 2001 Ieee International Workshop On Workload Characterization, Wwc 2001. 193-201. DOI: 10.1109/WWC.2001.990760  0.357
2001 Parikh A, Kandemir M, Vijaykrishnan N, Irwin MJ. VLIW scheduling for energy and performance Proceedings - Ieee Computer Society Workshop On Vlsi, Wvlsi 2001. 111-117. DOI: 10.1109/IWV.2001.923148  0.327
2001 Athavale R, Vijaykrishnan N, Kandemir M, Irwin MJ. Influence of array allocation mechanisms on memory system energy Proceedings - 15th International Parallel and Distributed Processing Symposium, Ipdps 2001. DOI: 10.1109/IPDPS.2001.924930  0.358
2001 Kandemir M, Vijaykrishnan N, Irwin MJ, Ye W. Influence of compiler optimizations on system power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 801-804. DOI: 10.1109/92.974893  0.328
2001 Delaluz V, Kandemir M, Vijaykrishnan N, Sivasubramaniam A, Irwin MJ. Hardware and software techniques for controlling DRAM power modes Ieee Transactions On Computers. 50: 1154-1173. DOI: 10.1109/12.966492  0.441
2001 Radhakrishnan R, Vijaykrishnan N, John LK, Sivasubramaniam A, Rubio J, Sabarinathan J. Java runtime systems: Characterization and architectural implications Ieee Transactions On Computers. 50: 131-146. DOI: 10.1109/12.908989  0.42
2001 Kandemir M, Vijaykrishnan N, Irwin MJ, Kim HS. Experimental evaluation of energy behavior of iteration space tiling Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2017: 142-157. DOI: 10.1007/3-540-45574-4_10  0.355
2001 Delaluz V, Kandemir M, Vijaykrishnan N, Sivasubramaniam A, Irwin MJ. DRAM energy management using software and hardware directed power mode control Ieee High-Performance Computer Architecture Symposium Proceedings. 159-169.  0.3
2001 Kadayif I, Chinoda T, Kandemir M, Vijaykrishnan N, Irwin MJ, Sivasubramaniam A. vEC: Virtual energy counters Acm Sigplan/Sigsoft Workshop On Program Analysis For Software Tools and Engineering. 28-31.  0.307
2001 Kim HS, Vijaykrishnan N, Kandemir M, Irwin MJ. A framework for energy estimation of VLIW architecture Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 40-45.  0.364
2001 Kadayif I, Kandemir M, Vijaykrishnan N, Irwin MJ, Ramanujam J. Morphable cache architectures: Potential benefits Sigplan Notices (Acm Special Interest Group On Programming Languages). 36: 128-137.  0.372
2001 Kandemir M, Vijaykrishnan N, Irwin MJ, Kim HS. Towards energy-aware iteration space tiling Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1985: 211-215.  0.318
2001 Tomar S, Kim S, Vijaykrishnan N, Kandemir M, Irwin MJ. Use of local memory for efficient Java execution Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 468-473.  0.318
2001 Kim S, Vijaykrishnan N, Kandemir M, Sivasubramaniam A, Irwin MJ, Geethanjali E. Power-aware partitioned cache architectures Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 64-67.  0.428
2001 Esakkimuthu G, Kim HS, Kandemir M, Vijaykrishnan N, Irwin MJ. Investigating memory system energy behavior using software and hardware optimizations Vlsi Design. 12: 151-165.  0.3
2000 Kim HS, Vijaykrishnan N, Kandemir M, Irwin MJ. Multiple access caches: Energy implications Proceedings - Ieee Computer Society Workshop On Vlsi 2000: System Design For a System-On-Chip Era, Iwv 2000. 53-58. DOI: 10.1109/IWV.2000.844530  0.389
2000 Parikh A, Kandemir M, Vijaykrishnan N, Irwin MJ. Instruction scheduling based on energy and performance constraints Proceedings - Ieee Computer Society Workshop On Vlsi 2000: System Design For a System-On-Chip Era, Iwv 2000. 37-42. DOI: 10.1109/IWV.2000.844527  0.392
2000 Radhakrishnan R, Vijaykrishnan N, John LK, Sivasubramaniam A. Architectural issues in Java runtime systems Ieee High-Performance Computer Architecture Symposium Proceedings. 387-398.  0.314
2000 Esakkimuthu G, Vijaykrishnan N, Kandemir M, Irwin MJ. Memory system energy: Influence of hardware-software optimizations Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 244-246.  0.337
2000 Ye W, Vijaykrishnan N, Kandemir M, Irwin MJ. Design and use of SimplePower: a cycle-accurate energy estimation tool Proceedings - Design Automation Conference. 340-345.  0.373
2000 Parikh A, Kandemir M, Vijaykrishnan N, Irwin MJ. Energy-aware instruction scheduling Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1970: 335-344.  0.335
2000 Delaluz V, Kandemir M, Vijaykrishnan N, Irwin MJ. Energy-oriented compiler optimizations for partitioned memory architectures Proceedings of the International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 138-147.  0.351
2000 Irwin MJ, Kandemir M, Vijaykrishnan N, Sivasubramaniam A. A holistic approach to system level energy optimization Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1918: 88-107.  0.306
2000 Radhakrishnan R, Vijaykrishnan N, John LK, Sivasubramaniam A. Architectural issues in Java runtime systems Ieee High-Performance Computer Architecture Symposium Proceedings. 387-398.  0.314
2000 Kim HS, Irwin MJ, Vijaykrishnan N, Kandemir M. Effect of compiler optimizations on memory energy Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 663-672.  0.355
2000 Vijaykrishnan N, Kandemir M, Irwin MJ, Kim HS, Ye W. Energy-driven integrated hardware-software optimizations using SimplePower Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 95-106.  0.353
1998 Krishna V, Ranganathan N, Vijaykrishnan N. Energy efficient scheduling scheme for signal processing applications Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 1057-1061.  0.304
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