Timothy Sherwood - US grants

This project focuses on improvements in upper division chemistry laboratories that would be fostered by the acquisition of a GC-ion trap mass spectrometer. In the upper division laboratories, the students perform comprehensive investigations beyond what is normally fond in many 'cookbook" type laboratory experiments. Each project lasts for two to four weeks, and includes some library research, sample preparation, and method development. The GC-MS is an integral part in several of these laboratory projects. The mass spectrometry of large biomolecules has become an increasingly powerful bioanalytical technique. Due to the size and cost of the necessary instrumentation, biological mass spectrometry is absent from most undergraduate curricula. In this project an experiment is being developed using the GC-ion trap that integrates the methodology of bioanalytical mass spectrometry into the course curriculum. Undergraduate research projects focusing on GC-MS method development and gas-phase thermochemistry are also underway. Arkansas's abundant natural resources foster many opportunities for environmentally related research projects. One example focuses on relating the aromatics emanating from various bird nests to the senses of predators. We also are utilizing the GC-ion trap mass spectrometer in the organic laboratory to aid in the identification products from organic syntheses.

CAREER: Architectural Support for Online Security Analysis
Abstract

A pressing problem facing modern computer system design is how to ensure that computers connected to the network are safe from attack. The research will investigate computer architectures that enable a new generation of network security devices capable of detecting suspicious network behavior and known attacks. Several different security applications are characterized by requiring the frequent access and maintenance of large amounts of state, such as large lookup tables, on every byte or packet, with worst-case bounds on throughput. Our architecture will take advantage of many small, wide word, on-chip memories to rapidly traverse large graph structures that are not well supported on current existing or proposed machines. This approach results in significant reduction in memory usage and increase in throughput. Such architecture could result in a new generation of devices capable of significantly reducing the damages caused by viruses, worms, and malicious attacks. The development of a functional prototype will enable both researchers and students to study the internal dynamics a network under attack, and the architectural challenges it presents.

NSF 0524771

CT-T: Collaborative Research: Adaptive Security and Separation in Reconfigurable Hardware

PI: Timothy Sherwood, University of California-Santa Barbara, Cynthia Irvine, Naval Postgraduate School

From Bluetooth transceivers to the NASA Mars Rover, reconfigurable circuits have become one of the mainstays of embedded design. Combining the high computational performance of specialized circuits with the re-programmability of software, these devices are quickly becoming ubiquitous. Unfortunately, if unprotected, this reconfigurability could be exploited to disrupt critical operations, snoop on supposedly secure channels, or even to physically melt a device. However, a new approach to controlling changes to the hardware logic promises to overcome these problems. In addition, the innate malleability of this hardware presents the opportunity for hardware enforcement of adaptive security policies. For example, in an emergency, trusted individuals may need to override the nominal security policy. Thus, the reconfigurable component may provide a highly trusted mechanism for secure functionality in changing environments.

This research aims to close a gaping security hole in our nation's information infrastructure by enhancing the logical structure and internal management of reconfigurable hardware to enforce a dynamic information protection policy. Specifically, this research will: (1) discover hardware synthesis and static validation methods that will ensure that only secure and non-destructive configurations can be loaded, (2) develop new reconfigurable structures capable of securely mediating run-time access to shared resources through the use of hardware-compiled formal access policy languages, and (3) establish a firm foundation for trustworthy dynamic policy enforcement through ontological analysis, formal modeling and the development of management mechanisms integrating the results of the first two activities.

CCF-0702798

Mimir: A Geometric Approach to Multi-dimensional Program Profiling Architectures

Timothy P. Sherwood

While mixed static-dynamic program analysis can be done completely in software through binary instrumentation, the amount of analysis that can be done at test-time is bounded by the performance impact that can be tolerated. The end goal of the Mimir project is to enable a new breed of hardware/software analysis tools, for researchers and system builders that can sift through on-line profile data at unprecedented speeds, yielding a highly accurate and timely image of computer system execution. The cross-layer approach to be investigated combines the raw computational ability of custom architectures with the formal guarantees provided by carefully crafted stream algorithms. At a high level, the proposed algorithmic approach to profiling is grounded in geometry, implicitly motivated by the belief that many profiling patterns, trends, or anomalies have natural geometric representations that become discernible under a geometric lens. At a low level, novel programmable hardware methods will provide a scalable and high performance substrate onto which these stream algorithms can be mapped. The combination of these two methods will allow online monitors to make streaming queries over live data at unprecedented speeds with the goal of enabling a new class of previously intractable dynamic analysis methods.

Proposal ID: 0811880
PI Name: Kaustav Banerjee
Institution: University of California-Santa Barbara
Title: A Collaborative Framework for Design and Fabrication of Metallic Carbon Nanotube based Interconnect Structures for VLSI Circuits and Systems Applications

ABSTRACT
The semiconductor industry is confronting an acute problem in the interconnect area due to the limited current carrying capability of copper wires, which are presently used to connect billions of transistors in every integrated circuit (IC) including microprocessors that are vital for information transmission, processing and storage. As IC feature sizes continue to be scaled below 45 nanometer, copper wires exhibit significant ?size effects? resulting in a sharp rise in their resistivity, which, in turn, has adverse impact both on their performance as well as reliability---in the form of current carrying capacity. This limitation of copper interconnects has been recently highlighted by various leading semiconductor companies around the world as well as in the International Technology Roadmap for Semiconductors (ITRS), and threatens to slow down or even stall the traditional growth of the semiconductor and related industries. Hence, it is critical to identify and develop new interconnect solutions.

Carbon nanotubes, tiny nanostructures 80,000 times narrower than a human hair, are known to have amazing electrical, thermal and mechanical properties, and can potentially address the challenges faced by copper and thereby extend the lifetime of ?electrical interconnects?. Most of these outstanding properties arise from the ?low-dimensionality? of CNTs---since they are essentially 1-dimensional structures. The investigators seek to, for the first time, understand how these tiny structures can be efficiently integrated into microprocessors and other circuitry to address the dire need for faster and more reliable on-chip wiring. The CNT interconnect structures also offer exciting prospects for design of ultra high-density energy storage elements (such as capacitors and inductors), as well as various system-level architectural innovations.

This collaborative four-year project brings together a team of scientists and engineers for addressing the key scientific and engineering challenges associated with the design and fabrication of CNT interconnect structures for various circuits and systems applications. The investigators employ an interdisciplinary approach that combines innovative process technology and circuit/system architecture development supported by rigorous modeling, analysis, and metrology techniques. This presents an outstanding opportunity to truly demonstrate the prospects of CNTs in overcoming one of the major limitations of nanometer scale ICs, and is expected to have wide implications for the semiconductor industry. This research will help scaling of CMOS circuits to its ultimate limits and also open new opportunities in mixed-signal, analog and radio-frequency (RF) signal processing applications as well as in 3-dimensional integrated circuit design, thereby maintaining U.S. competitiveness in the worldwide semiconductor market. Broader impact of the research includes emerging off-chip applications of carbon nanotubes as ?solder bumps? and also as an excellent thermal interface material for heat removal from chips and printed circuit boards. The overall program also ties research to education at all levels (K-12, undergraduate, graduate, continuing-education) partly via participation in programs designed by education professionals, besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.

This research project studies the feasibility of digital, programmable, software-based control of micro-electromechanical systems (MEMS). MEMS are extremely small physical structures capable of movement, lithographically combined with similarly-scaled electrical circuits to produce micron-scale mechanical devices. Examples of MEMS are tunneling accelerometers, gyroscopes, and micro-mirrors. Currently, analog controllers are used to control MEMS because of the very small time constants required to control devices at this scale. This project has the goal of developing a new style of embedded, software feedback controllers that communicate to sigma-delta over-sampled analog interfaces via high sample rate delta encoding. These designs are the result of research in metric-based controller decomposition that specifically seeks to achieve the potential of multi-rate, over-sampled signal processing. Direct benefits of this work are digital controllers suitable for MEMS integration that match the requirements and potential of these designs, delivering performance/power ratios that are not possible currently. Although the chosen implementation strategy is FPGA based, the decomposition strategy should lead to very small designs, competitive in power to current low-end microprocessors, with dozens to hundreds of times the performance achieved by current software based control using digital signal processing (DSP) platforms. The broader impact of this research project is the development of practical techniques for the design and modeling of over-sampled controllers for MEMS devices that will have direct impact in medical prosthetics, distributed sensing, and the vast range of applications that can benefit from battery-operated sensor array devices. The project seeks educational impact in the form of graduate curriculum development and of efforts to enable substantive undergraduate involvement in research.

While hardware resources for computation and data storage are now abundant,
economic factors prevent specialized hardware security mechanisms from being
integrated into commodity parts. System owners are caught between the need to exploit
cheap, fast, commodity microprocessors and the need to ensure that critical security
properties hold.

This research will explore a novel way to augment commodity hardware after fabrication
to enhance secure operation. The basic approach is to add a separate silicon layer,
housing select security features, onto an existing integrated circuit. This 3-D Integration
decouples the function and economics of security policy enforcement from the
underlying computing hardware. As a result, security enhancements are manufacturing
options applicable only to those systems that require them, which resolves the
economic quandary. We plan to identify a minimal and realizable set of circuit-level
security capabilities enabled by this approach, which can be judiciously controlled by
the software layers. This will significantly assist in reducing both the software complexity
often associated with security mechanisms and system vulnerabilities.
This research introduces a fundamentally new method to incorporate security
mechanisms into hardware and has the potential to significantly shift the economics of
trustworthy systems. A broader impact will result through collaborative and educational
activities. Graduate and undergraduate student research associates will transfer
knowledge to future teachers, researchers and Information Assurance professionals;
and project publications will provide direct technical transfer to the embedded-systems
and hardware-design communities.

Computer performance has doubled many times over during the past 40 years, but the very techniques used to achieve these performance gains have made it increasingly difficult to build systems that are provably safe, secure, or reliable. This fact significantly impedes progress in the development of our most safety-critical embedded systems such as those found in medical, avionic, automotive, and military systems. A transformation in the way that these systems are created is needed, one that uses new hardware design techniques, computer architectures, and programming languages to create classes of hardware/software systems with formal and provable safety properties that are verifiable all the way down to the implementation level of bits and logic gates.

This research will change the way that hardware and embedded systems designers approach the problem of provable properties, enabling them to directly control and analyze the system at the lowest level and to statically determine if their designs are in compliance with a given policy. For example, if a system must be real-time this property can be verifiable for a full system, from gates to software, by ensuring that the architecture design carefully manages interference through a set of new hardware primitives, software designed to exploit these new primitives, specialized hardware analysis tools, and new design languages. To ensure this technology will have impact beyond academia the PIs are making these new technologies available and accessible through easy to use tools, continuing to include undergraduates at all levels of research to help train a new generation of engineers capable of designing safety-critical systems, and integrating concepts from information assurance into their extensive outreach activities. Over the long term this research will help create the skills and tools that embedded system engineers need to evaluate the trustworthiness of their systems, and it will ease the development of those critical systems on which we all depend on for our safety and livelihood.

As computing devices continue to be embedded in more and more physical devices, they are now privy to the most confidential information about our lives. The ability to safely keep a secret in memory is central to the vast majority of security systems, but storing and erasing these secrets is a difficult problem in the face of an attacker who can obtain unrestricted physical access to these devices and the underlying hardware. Depending on the memory technology, the very act of storing a 1 instead of a 0 can have physical side effects measurable even after the power has been cut. Through the development of a new class of architectures that measurably increase the difficulty of physical analysis this project is enabling systems that can be trusted even when physical control of the system is ceded to an adversary. Initial results indicate that the creation of an efficient scheme for memory protection is possible under which, even if an adversary is able to inspect the value of a stored bit with a probabilistic error of only 5%, the system will be able to prevent that adversary from learning any information about the original un-coded bits with 99.9999999999% probability. Over the long term this research will help to create the skills and tools that cyber-physical system engineers will need to develop pervasive trustworthy systems, and to ease the development of those mission critical systems that we all depend on for our safety and livelihood.

Computer systems increasingly perform operations on critical and confidential data. Despite best efforts to protect this information, the side effects of computations using this data, e.g., the computation time, the power consumption, electromagnetic radiation, thermal emanations, and acoustics, can be used to decipher secret information even when it is encrypted. Power analysis attacks are particularly powerful and have been shown time and again to be able to quickly and reliably extract the most critical information from otherwise secure devices including smart cards, RFIDs, microcontrollers, microprocessors, and other computing hardware.

Drawing inspiration from the human body, the proposed research will develop new techniques to mitigate power analysis attacks through a technique called computational blinking. An average person blinks 15-20 times per minute; in fact our eyes are closed around 10% of our waking hours due to blinking. With each and every blink, sections of our brain are momentarily "powered off," yet we are rarely even aware of these near continuous interruptions. Our techniques replicate this same, seemingly imperceivable interleaving of "connected" and "disconnected" states in a computer system through the dynamic reconfiguration of the electrical network powering a device. During a computational blink, a portion of the processor is momentarily electrically disconnected from the rest of the system making it more difficult to modify or examine the side effects (e.g., power consumption) of that computation. Our innovative circuits, architectures, run-time systems, programming frameworks, design tools, and measurement methodologies make these intermittent disconnections just as imperceivable in computing systems.

The main goal of this project is to develop analog computing circuits that will greatly exceed their digital counterparts in energy-efficiency, speed, and density by employing emerging nonvolatile memory devices. Though analog circuits have been around for a long time, their applications in computing have been rather limited, largely due to the lack of efficient implementations of analog weights. This impediment could be overcome now due to the rapid progress in the emerging nonvolatile memory devices, such as metal-oxide memristors, which are the focus in this project. The analog memory functionality of memristors, combined with high retention and sub-10-nm scaling prospects, might for the first time enable extremely fast and energy-efficient analog implementations of many core operations, such as vector-by-matrix multiplication, which are central to many existing and emerging future applications such as internet-of-the-things and sensor networks, robotics, and energy efficient neuromorphic systems. The results of the proposed research will be integrated into educational curriculum and will help to train material science and electrical engineering students of all levels in this exciting field.

The main caveat of the considered analog circuits is their limited operation accuracy, primarily due to the noise and variability in memory devices. The mitigation of this challenge by several means will be one of the main focuses of the project, and will be addressed with highly-interconnected research effort across device, circuit, and architectural layers. At the device level, detailed electrical characterization of analog operation and ways to improve it via material engineering, optimization of electrical stress, and development of efficient tuning algorithms to cope with device variations will be explored. Guided by experimentally-verified device models, the design of several representative analog computing circuits will be optimized. Circuit modeling tools will be developed to capture rich design trade offs in area, speed, energy efficiency, and precision, calibrated on experimental results from wafer-scale integrated memristor circuits, and used for detailed comparison with state-of-the-art digital counterparts. Finally, accurate circuit models will guide exploration of circuit architectures that mitigate limitations of analog computing and assist with detailed system level simulations.

Aggressive technology scaling into the deep sub-micron (DSM) regime has been accompanied by a dramatic increase in transistor densities with shrinking transistor feature size that approaches the physical limits, resulting in major economic and technical challenges that are expected to hinder the continued scaling of traditional Complimentary Metal-Oxide Semiconductor (CMOS) technology. This has resulted in the trends of searching for alternative emerging technologies that can continue the performance/power improvement for computing systems. As the underlying emerging technologies continue to evolve, it has become imperative for computer engineers to translate the potential of such emerging devices into circuits and architecture designs. Such new circuits and architecture designs will face multiple challenges ranging from the modeling/abstraction and simulation of such emerging technologies, to the complexity due to the sheer volume of nanodevices that will have to be integrated for complex functionality.

The proposing team is exploring multiple emerging technologies (including three-dimensional integration, emerging non-volatile memory, and nanophotonics) with a comprehensive coverage of innovative work in the modeling, design analysis, simulation, verification, testing, and evaluation of circuits and architectures constructed out of emerging technologies, to overcome all the CMOS scaling limits. Efficient design and use of future system architectures using emerging technologies will be vital to the future of computing. The acquired equipment and the chip prototyping will be used to train graduate students and undergraduate students including those from under-represented groups advised by the PIs (women and minority students) to gain expertise in the area of computer architecture, Very Large-Scale Integration (VLSI), and device fabrication. Teaching material and lab modules will be developed for several courses and made available on the web for wider dissemination. Ongoing collaborations with industry partners and national labs in current NSF-funded research will be used for transfer of technology.

In addition to their usual roles in our everyday lives computers also play invisible safety-critical roles. They prevent the brakes in cars from locking up, fly our airplanes through dense air traffic and around large storms, manage our electrical and water systems, and even control the beating of patients' hearts. Unfortunately, it still remains difficult to build computer systems for which one can say anything definitive about reliability of such operation. This project attempts to change the way in which critical computer systems are designed and analyzed. The technologies created will be available and accessible through open repositories, the development of those technologies will provide both undergraduate and graduate students numerous training opportunities, the most exciting ideas will be used in outreach efforts to help reach new generations of engineers, and in the end will help to develop a national community of embedded systems engineers with the skills and tools necessary to implement safe and reliable systems.

To achieve this vision of more robust computer controlled systems we need new approaches to creating them that includes both the hardware and the software together. Traditional computer hardware is built for speed and efficiency at all costs, but often we have more than enough speed and efficiency to get a job done. Instead, we need systems that, while remaining quite efficient, also are far easier to understand and reason about. Building on top of powerful theories of computation (such as lambda-calculus) a new computer system, where every action it takes corresponds directly to a tractable set of equations, can be created. Rather than try and solve the resulting equations by hand, this project reconsiders the way computer processors are designed from the ground up so that they work in perfect harmony with state-of-the-art computer-automated theorem provers. To demonstrate that this approach is actually useful on real world problems the investigators are building a completely new computer system around this approach with all of the hardware design, computer languages, and operating system-like software needed.

The ever-increasing demand for optimized large-scale computing systems puts pressure on attaining significant improvements in automated design optimization and synthesis tools. This project aims to overcome the limitations of prior approaches through a tighter integration of optimization and synthesis algorithms leveraging advances in modern automated reasoning systems. The project demonstrates the power of Satisfiability Modulo Theories (SMT)-based synthesis combined with emerging research in Optimization Modulo Theories (OMT).

The project explores advances in both theory and practice, with research demonstrations integrated into CVC4, the only SMT solver today providing synthesis features. In particular, CVC4 is being extended with optimization capabilities, making it the first automated reasoning tool capable of performing synthesis and optimization together. The resulting extensible framework enables system design for emerging technologies which often require reasoning over non Boolean (and mixed) primitives. The extensibility and generality of the approach charts a new direction of research at the intersection of synthesis and optimization, leads towards more scalable and complex system design, and allows optimization over a broader class of objectives including security and safety.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.