Harold W. Cain, Ph.D.
Affiliations: | 2004 | University of Wisconsin, Madison, Madison, WI |
Area:
Computer ScienceGoogle:
"Harold Cain"Parents
Sign in to add mentor| Mikko H. Lipasti | grad student | 2004 | UW Madison | |
| (Detecting and exploiting causal relationships in hardware shared -memory multiprocessors.) | ||||
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Publications
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| Cain HW, Lipasti MH. (2012) Edge chasing delayed consistency: Pushing the limits of weak memory models Splash 2012: Races 2012 - Proceedings of the 2012 Acm Workshop On Relaxing Synchronization For Multicore and Manycore Scalability. 15-24 |
| Daly D, Cain HW. (2012) Cache restoration for highly partitioned virtualized systems Proceedings - International Symposium On High-Performance Computer Architecture. 225-234 |
| Cain HW, Nagpurkar P. (2010) Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor Ispass 2010 - Ieee International Symposium On Performance Analysis of Systems and Software. 203-212 |
| Wu P, Michael MM, Von Praim C, et al. (2009) Compiler and runtime techniques for software transactional memory optimization Concurrency Computation Practice and Experience. 21: 7-23 |
| Caşcaval C, Blundell C, Michael M, et al. (2008) Software transactional memory Queue. 6: 46-58 |
| Cascaval C, Blundell C, Michael M, et al. (2008) Software transactional memory: Why is it only a research toy? Communications of the Acm. 51: 40-46 |
| Nagpurkar P, Cain HW, Serrano M, et al. (2007) Call-chain software instruction prefetching in J2EE server applications Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 140-149 |
| Von Praun C, Cain HW, Choi JD, et al. (2006) Conditional memory ordering Proceedings - International Symposium On Computer Architecture. 2006: 41-52 |
| Cain HW, Lipasti MH, Nair R. (2004) Constraint graph analysis of multithreaded programs Journal of Instruction-Level Parallelism. 6 |
| Cain HW, Lipasti MH. (2004) Memory ordering: A value-based approach Ieee Micro. 24: 110-117 |