Karthikeyan Lingasubramanian, Ph.D.
Affiliations: | 2010 | University of South Florida, Tampa, FL, United States |
Area:
Electronics and Electrical Engineering, Computer Engineering, Computer ScienceGoogle:
"Karthikeyan Lingasubramanian"Parents
Sign in to add mentorSanjukta Bhanja | grad student | 2010 | University of South Florida | |
(Probabilistic error analysis models for nano-domain VLSI circuits.) |
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Publications
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Kakkara V, Balasubramanian K, Yamuna B, et al. (2020) A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study. Peerj. Computer Science. 6: e250 |
Gunti NB, Lingasubramanian K. (2017) Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits Integration. 59: 233-242 |
Gunti NB, Khatri A, Lingasubramanian K. (2015) Realizing a security aware triple modular redundancy scheme for robust integrated circuits Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc. 2015 |
Lingasubramanian K, Alam SM, Bhanja S. (2011) Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis Microelectronics Reliability. 51: 485-501 |
Lingasubramanian K, Bhanja S. (2009) An error model to study the behavior of transient errors in sequential circuits Proceedings: 22nd International Conference On Vlsi Design - Held Jointly With 7th International Conference On Embedded Systems. 485-490 |
Rejimon T, Lingasubramanian K, Bhanja S. (2009) Probabilistic error modeling for nano-domain logic circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 55-65 |
Lingasubramanian K, Bhanja S. (2009) Work in progress - An education module on engineering ethics concentrating on environment friendly engineering for computer engineers Proceedings - Frontiers in Education Conference, Fie |
Shareef A, Lingasubramanian K, Bhanja S. (2008) Selective redundancy: Evaluation of temporal reliability enhancement scheme for nanoelectronic circuits 2008 8th Ieee Conference On Nanotechnology, Ieee-Nano. 895-898 |
Lingasubramanian K, Bhanja S. (2007) Probabilistic maximum error modeling for unreliable logic circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 223-226 |
Lingasubramanian K, Bhanja S. (2007) Probabilistic error modeling for sequential logic 2007 7th Ieee International Conference On Nanotechnology - Ieee-Nano 2007, Proceedings. 616-620 |