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Karthikeyan Lingasubramanian, Ph.D. - Publications

Affiliations: 
2010 University of South Florida, Tampa, FL, United States 
Area:
Electronics and Electrical Engineering, Computer Engineering, Computer Science
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12 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Kakkara V, Balasubramanian K, Yamuna B, Mishra D, Lingasubramanian K, Murugan S. A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study. Peerj. Computer Science. 6: e250. PMID 33816902 DOI: 10.7717/Peerj-Cs.250  0.47
2017 Gunti NB, Lingasubramanian K. Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits Integration. 59: 233-242. DOI: 10.1016/J.Vlsi.2017.06.002  0.44
2015 Gunti NB, Khatri A, Lingasubramanian K. Realizing a security aware triple modular redundancy scheme for robust integrated circuits Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc. 2015. DOI: 10.1109/VLSI-SoC.2014.7004183  0.432
2011 Lingasubramanian K, Alam SM, Bhanja S. Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis Microelectronics Reliability. 51: 485-501. DOI: 10.1016/J.Microrel.2010.07.156  0.694
2009 Lingasubramanian K, Bhanja S. An error model to study the behavior of transient errors in sequential circuits Proceedings: 22nd International Conference On Vlsi Design - Held Jointly With 7th International Conference On Embedded Systems. 485-490. DOI: 10.1109/VLSI.Design.2009.73  0.721
2009 Rejimon T, Lingasubramanian K, Bhanja S. Probabilistic error modeling for nano-domain logic circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 55-65. DOI: 10.1109/Tvlsi.2008.2003167  0.718
2009 Lingasubramanian K, Bhanja S. Work in progress - An education module on engineering ethics concentrating on environment friendly engineering for computer engineers Proceedings - Frontiers in Education Conference, Fie. DOI: 10.1109/FIE.2009.5350492  0.406
2008 Shareef A, Lingasubramanian K, Bhanja S. Selective redundancy: Evaluation of temporal reliability enhancement scheme for nanoelectronic circuits 2008 8th Ieee Conference On Nanotechnology, Ieee-Nano. 895-898. DOI: 10.1109/NANO.2008.268  0.653
2007 Lingasubramanian K, Bhanja S. Probabilistic maximum error modeling for unreliable logic circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 223-226. DOI: 10.1145/1228784.1228842  0.719
2007 Lingasubramanian K, Bhanja S. Probabilistic error modeling for sequential logic 2007 7th Ieee International Conference On Nanotechnology - Ieee-Nano 2007, Proceedings. 616-620. DOI: 10.1109/NANO.2007.4601266  0.714
2006 Bhanja S, Lingasubramanian K, Ranganathan N. A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic Bayesian networks Acm Transactions On Design Automation of Electronic Systems. 11: 773-796. DOI: 10.1145/1142980.1142990  0.67
2005 Bhanja S, Lingasubramanian K, Ranganathan N. Estimation of switching activity in sequential circuits using dynamic Bayesian Networks Proceedings of the Ieee International Conference On Vlsi Design. 586-591. DOI: 10.1109/ICVD.2005.93  0.674
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