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Ashok Jagannathan, Ph.D. - Publications

Affiliations: 
2005 University of California, Los Angeles, Los Angeles, CA 
Area:
Computer system architecture, energy-efficient computing, reconfigurable computing, electronic design automation, fault-tolerant design of VLSI systems, design for nanotechnologies, design and analysis of algorithms
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5 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2007 Cong J, Han G, Jagannathan A, Reinman G, Rutkowski K. Accelerating sequential applications on CMPs using core spilling Ieee Transactions On Parallel and Distributed Systems. 18: 1094-1107. DOI: 10.1109/Tpds.2007.1085  0.483
2006 Cong J, Jagannathan A, Ma Y, Reinman G, Wei J, Zhang Y. An automated design flow for 3D microarchitecture evaluation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 384-389.  0.325
2005 Jagannathan A, Yang HH, Konigsfeld K, Milliron D, Mohan M, Romesis M, Reinman G, Cong J. Microarchitecture evaluation with floorplanning and interconnect pipelining Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: I8-I15.  0.517
2005 Cong J, Fan Y, Han G, Jagannathan A, Reinman G, Zhang Z. Instruction set extension with shadow registers for configurable processors Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 99-106.  0.369
2003 Cong J, Jagannathan A, Reinman G, Romesis M. Microarchitecture evaluation with physical planning Proceedings - Design Automation Conference. 32-35.  0.513
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