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Scott Hauck - Publications

Affiliations: 
Northwestern University, Evanston, IL 
Area:
Electronics and Electrical Engineering, Computer Science
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68 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2022 Deiana AM, Tran N, Agar J, Blott M, Di Guglielmo G, Duarte J, Harris P, Hauck S, Liu M, Neubauer MS, Ngadiuba J, Ogrenci-Memik S, Pierini M, Aarrestad T, Bähr S, et al. Applications and Techniques for Fast Machine Learning in Science. Frontiers in Big Data. 5: 787421. PMID 35496379 DOI: 10.3389/fdata.2022.787421  0.305
2019 Duarte J, Harris P, Hauck S, Holzman B, Hsu S, Jindariani S, Khan S, Kreis B, Lee B, Liu M, Lončar V, Ngadiuba J, Pedro K, Perez B, Pierini M, et al. FPGA-accelerated machine learning inference as a service for particle physics computing Arxiv: Data Analysis, Statistics and Probability. 3: 13. DOI: 10.1007/S41781-019-0027-2  0.412
2015 Putnam A, Caulfield AM, Chung ES, Chiou D, Constantinides K, Demme J, Esmaeilzadeh H, Fowers J, Gopal GP, Gray J, Haselman M, Hauck S, Heil S, Hormati A, Kim JY, et al. A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services Ieee Micro. 35: 10-22. DOI: 10.1145/2996868  0.46
2015 Wood A, Hauck S. Offset pipelined scheduling: Conditional branching for CGRAs Proceedings - 2015 Ieee 23rd Annual International Symposium On Field-Programmable Custom Computing Machines, Fccm 2015. 227-230. DOI: 10.1109/FCCM.2015.51  0.39
2015 Gabrielli A, Backhaus M, Balbi G, Bindi M, Chen SP, Falchieri D, Flick T, Hauck S, Hsu SC, Kretz M, Kugel A, Lama L, Travaglini R, Wensing M. Firmware development and testing of the ATLAS Pixel Detector/IBL ROD card Journal of Instrumentation. 10. DOI: 10.1088/1748-0221/10/03/C03037  0.391
2014 Kim JY, Hauck S, Burger D. A scalable multi-engine Xpress9 compressor with asynchronous data transfer Proceedings - 2014 Ieee 22nd International Symposium On Field-Programmable Custom Computing Machines, Fccm 2014. 161-164. DOI: 10.1109/FCCM.2014.49  0.362
2014 Balbi G, Bindi M, Falchieri D, Gabrielli A, Travaglini R, Chen SP, Hsu SC, Hauck S, Kugel A. Commissioning of the read-out driver (ROD) card for the ATLAS IBL detector and upgrade studies for the pixel Layers 1 and 2 Nuclear Instruments and Methods in Physics Research, Section a: Accelerators, Spectrometers, Detectors and Associated Equipment. 765: 232-234. DOI: 10.1016/J.Nima.2014.05.034  0.32
2012 Haselman MD, Pasko J, Hauck S, Lewellen TK, Miyaoka RS. FPGA-based pulse pile-up correction with energy and timing recovery Ieee Transactions On Nuclear Science. 59: 1823-1830. DOI: 10.1109/Tns.2012.2207403  0.399
2012 Wood A, Knight A, Ylvisaker B, Hauck S. Multi-kernel floorplanning for enhanced CGRAS Proceedings - 22nd International Conference On Field Programmable Logic and Applications, Fpl 2012. 157-164. DOI: 10.1109/FPL.2012.6339255  0.307
2012 Panda R, Ebeling C, Hauck S. Adding dataflow-driven execution control to a coarse-grained reconfigurable array Proceedings - 22nd International Conference On Field Programmable Logic and Applications, Fpl 2012. 353-360. DOI: 10.1109/FPL.2012.6339204  0.368
2011 Papadimitriou K, Dollas A, Hauck S. Performance of Partial Reconfiguration in FPGA systems: A survey and a cost model Acm Transactions On Reconfigurable Technology and Systems. 4. DOI: 10.1145/2068716.2068722  0.414
2011 Johnson-Williams NG, Miyaoka RS, Li X, Lewellen TK, Hauck S. Design of a real time FPGA-based three dimensional positioning algorithm Ieee Transactions On Nuclear Science. 58: 26-33. DOI: 10.1109/Tns.2010.2093909  0.431
2011 Panda R, Hauck S. Dynamic communication in a coarse grained reconfigurable array Proceedings - Ieee International Symposium On Field-Programmable Custom Computing Machines, Fccm 2011. 25-28. DOI: 10.1109/FCCM.2011.47  0.316
2011 Chen ZH, Su AWY, Sun MT, Hauck S. Accelerating statistical LOR estimation for a high-resolution PET scanner using FPGA devices and a high level synthesis tool Proceedings - Ieee International Symposium On Field-Programmable Custom Computing Machines, Fccm 2011. 105-108. DOI: 10.1109/FCCM.2011.15  0.335
2010 Dewitt D, Johnson-Williams NG, Miyaoka RS, Li X, Lockhart C, Lewellen TK, Hauck S. Design of an FPGA-Based Algorithm for Real-Time Solutions of Statistics-Based Positioning. Ieee Transactions On Nuclear Science. 57: 71-77. PMID 21197135 DOI: 10.1109/Tns.2009.2030581  0.472
2009 Johnson-Williams NG, Miyaoka RS, Li X, Lewellen TK, Hauck S. Design of a Real Time FPGA-based Three Dimensional Positioning Algorithm. Ieee Nuclear Science Symposium Conference Record. Nuclear Science Symposium. 2009: 1082-3654. PMID 20625466 DOI: 10.1109/NSSMIC.2009.5401848  0.32
2008 Compton K, Hauck S. Automatic design of reconfigurable domain-specific flexible cores Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 493-503. DOI: 10.1109/Tvlsi.2007.915439  0.712
2008 Beauchamp MJ, Hauck S, Underwood KD, Hemmert KS. Architectural modifications to enhance the floating-point performance of FPGAs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 177-187. DOI: 10.1109/Tvlsi.2007.912041  0.474
2008 Eguro K, Hauck S. Simultaneous retiming and placement for pipelined netlists Proceedings of the 16th Ieee Symposium On Field-Programmable Custom Computing Machines, Fccm'08. 139-148. DOI: 10.1109/FCCM.2008.21  0.415
2008 Eguro K, Hauck S. Enhancing timing-driven FPGA placement for pipelined netlists Proceedings - Design Automation Conference. 34-37. DOI: 10.1109/DAC.2008.4555777  0.367
2008 Fry TW, Hauck S. SPIHT Image Compression Reconfigurable Computing. 565-590. DOI: 10.1016/B978-012370522-8.50036-4  0.361
2008 Eguro K, Hauck S. Fast Compilation Techniques Reconfigurable Computing. 411-433. DOI: 10.1016/B978-012370522-8.50027-3  0.403
2008 Hauck S, DeHon A. Reconfigurable Computing Reconfigurable Computing.  0.514
2007 Holland M, Hauck S. Automatic creation of domain-specific reconfigurable CPLDs for SoC Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 291-295. DOI: 10.1109/Tcad.2006.887926  0.506
2007 Compton K, Hauck S. Automatic design of area-efficient configurable ASIC cores Ieee Transactions On Computers. 56: 662-672. DOI: 10.1109/Tc.2007.1035  0.723
2006 Leeser M, Hauck S, Tessier R. Field-programmable gate arrays in embedded systems Eurasip Journal On Embedded Systems. 2006. DOI: 10.1155/Es/2006/51312  0.338
2006 Sharma A, Ebeling C, Hauck S. PipeRoute: A pipelining-aware router for reconfigurable architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 518-532. DOI: 10.1109/Tcad.2005.853691  0.394
2006 Beauchamp MJ, Hauck S, Underwood KD, Hemmert KS. Architectural modifications to improve floating-point unit efficiency in FPGAS Proceedings - 2006 International Conference On Field Programmable Logic and Applications, Fpl. 515-520. DOI: 10.1109/FPL.2006.311260  0.403
2006 Beauchamp MJ, Hauck S, Underwood KD, Hemmert KS. Embedded floating-point units in FPGAs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 12-20.  0.42
2006 Holland M, Hauck S. Improving performance and robustness of domain-specific CPLDs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 50-59.  0.452
2005 Fry TW, Hauck SA. SPIHT image compression on FPGAs Ieee Transactions On Circuits and Systems For Video Technology. 15: 1138-1147. DOI: 10.1109/TCSVT.2005.852625  0.368
2005 Eguro K, Hauck SA. Resource allocation for coarse-grain FPGA development Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1572-1581. DOI: 10.1109/TCAD.2005.852291  0.343
2005 Chang ML, Hauck S. Précis: A usercentric word-length optimization tool Ieee Design and Test of Computers. 22: 349-361. DOI: 10.1109/Mdt.2005.92  0.435
2005 Sharma A, Hauck S. Accelerating FPGA routing using architecture-adaptive A* techniques Proceedings - 2005 Ieee International Conference On Field Programmable Technology. 2005: 225-232. DOI: 10.1109/FPT.2005.1568551  0.3
2005 Sharma A, Hauck S, Ebeling C. Architecture-adaptive routability-driven placement for FPGAS Proceedings - 2005 International Conference On Field Programmable Logic and Applications, Fpl. 2005: 427-432. DOI: 10.1109/FPL.2005.1515759  0.385
2005 Phillips S, Hauck S. Automating the layout of reconfigurable subsystems using circuit generators Proceedings - 13th Annual Ieee Symposium On Field-Programmable Custom Computing Machines, Fccm 2005. 2005: 203-212. DOI: 10.1109/FCCM.2005.24  0.479
2005 Eguro K, Hauck S, Sharma A. Architecture-adaptive range limit windowing for simulated annealing FPGA placement Proceedings - Design Automation Conference. 439-444.  0.332
2005 Sharma A, Ebeling C, Hauck S. Architecture adaptive routability-driven placement for FPGAs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 266.  0.37
2004 Hauck S, Fry TW, Hosler MM, Kao JP. The Chimaera Reconfigurable Functional Unit Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 206-217. DOI: 10.1109/Tvlsi.2003.821545  0.523
2004 Phillips S, Sharma A, Hauck S. Automating the layout of reconfigurable subsystems via template reduction Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3203: 857-861. DOI: 10.1109/FCCM.2004.19  0.485
2004 Sharma A, Compton K, Ebeling C, Hauck S. Exploration of pipelined FPGA interconnect structures Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 12: 13-22.  0.353
2004 Compton K, Hauck S. Flexibility measurement of domain-specific reconfigurable hardware Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 12: 155-161.  0.444
2004 Holland M, Hauck S. Automatic creation of reconfigurable PALs/PLAs for SoC Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3203: 536-545.  0.419
2003 Eguro K, Hauck S. Issues and approaches to coarse-grain reconfigurable architecture development Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2003: 111-120. DOI: 10.1109/FPGA.2003.1227247  0.4
2003 Compton K, Hauck S. Track placement: Orchestrating routing structures to maximize routability Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2778: 121-130.  0.302
2002 Compton K, Hauck S. Reconfigurable Computing: A Survey of Systems and Software Acm Computing Surveys. 34: 171-210. DOI: 10.1145/508352.508353  0.71
2002 Compton K, Li Z, Cooley J, Knol S, Hauck S. Configuration relocation and defragmentation for run-time reconfigurable computing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 209-220. DOI: 10.1109/Tvlsi.2002.1043324  0.718
2002 Fry TW, Hauck S. Hyperspectral image compression on reconfigurable platforms Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2002: 251-260. DOI: 10.1109/FPGA.2002.1106679  0.322
2002 Chang ML, Hauck S. Précis: A design-time precision analysis tool Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2002: 229-238. DOI: 10.1109/FPGA.2002.1106677  0.349
2002 Phillips S, Hauck S. Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 165-173.  0.409
2002 Li Z, Hauck S. Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 187-195.  0.387
2002 Compton K, Sharma A, Phillips S, Hauck S. Flexible routing architecture generation for domain-specific reconfigurable subsystems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2438: 59-68.  0.52
2001 Mulpuri C, Hauck S. Runtime and quality tradeoffs in FPGA placement and routing Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 29-36.  0.304
2001 Li Z, Hauck S. Configuration Compression for Virtex FPGAs Proceedings - 9th Annual Ieee Symposium On Field-Programmable Custom Computing Machines, Fccm 2001. 147-159.  0.425
2001 Compton K, Hauck S. Totem: Custom Reconfigurable Array Generation Proceedings - 9th Annual Ieee Symposium On Field-Programmable Custom Computing Machines, Fccm 2001. 111-119.  0.536
2000 Compton K, Cooley J, Knol S, Hauck S. Abstract: Configuration relocation and defragmentation for reconfigurable computing Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2000: 279-280. DOI: 10.1109/FPGA.2000.903415  0.517
2000 Li Z, Compton K, Hauck S. Configuration caching management techniques for reconfigurable computing Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2000: 22-36. DOI: 10.1109/FPGA.2000.903390  0.417
2000 Hauck S, Hosler MM, Fry TW. High-performance carry chains for FPGA's Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 138-147. DOI: 10.1109/92.831434  0.449
1999 Enos M, Hauck S, Sarrafzadeh M. Evaluation and optimization of replication algorithms for logic bipartitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1237-1248. DOI: 10.1109/43.784117  0.418
1999 Hauck S, Li Z, Schwabe E. Configuration compression for the Xilinx XC6200 FPGA Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1107-1113. DOI: 10.1109/43.775631  0.533
1999 Hauck S, Wilson WD. Abstract: Runlength compression techniques for FPGA configurations Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 286-287.  0.339
1998 Hauck S, Bordello G, Ebeling C. Mesh routing topologies for multi-FPGA systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 400-408. DOI: 10.1109/92.711311  0.474
1998 Hauck S. The roles of FPGA's in reprogrammable systems Proceedings of the Ieee. 86: 615-638. DOI: 10.1109/5.663540  0.466
1997 Hauck S, Borriello G. Pin assignment for multi-FPGA systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 956-964. DOI: 10.1109/43.658564  0.439
1997 Hauck S, Borriello G. An evaluation of bipartitioning techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 849-866. DOI: 10.1109/43.644609  0.38
1995 Borriello G, Ebeling C, Hauck SA, Burns S. The Triptych FPGA Architecture Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 491-501. DOI: 10.1109/92.475968  0.44
1995 Ebeling C, McMurchie L, Hauck SA, Burns S. Placement and Routing Tools for the Triptych FPGA Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 473-482. DOI: 10.1109/92.475966  0.488
1994 Hauck S, Burns S, Borriello G, Ebeling C. An FPGA for Implementing Asynchronous Circuits Ieee Design and Test of Computers. 11: 60-69. DOI: 10.1109/Mdt.1994.303848  0.508
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