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Patrick Ndai, Ph.D. - Publications

Affiliations: 
2009 Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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12 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2011 Kulkarni JP, Goel A, Ndai P, Roy K. A read-disturb-free, differential sensing 1R/1W Port, 8T bitcell array Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1727-1730. DOI: 10.1109/Tvlsi.2010.2055169  0.642
2010 Li J, Ndai P, Goel A, Salahuddin S, Roy K. Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1710-1723. DOI: 10.1109/Tvlsi.2009.2027907  0.643
2010 Ndai P, Goel A, Roy K. A scalable circuit-architecture co-design to improve memory yield for high-performance processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1209-1219. DOI: 10.1109/Tvlsi.2009.2022628  0.694
2010 Ndai P, Rafique N, Thottethodi M, Ghosh S, Bhunia S, Roy K. Trifecta: A nonspeculative scheme to exploit common, data-dependent subcritical paths Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 53-65. DOI: 10.1109/Tvlsi.2008.2007491  0.648
2009 Goel A, Ndai P, Kulkarni JP, Roy K. REad/access-preferred (REAP) SRAM - Architecture-aware bit cell design for improved yield and lower V MIN Proceedings of the Custom Integrated Circuits Conference. 503-506. DOI: 10.1109/CICC.2009.5280794  0.67
2009 Li J, Ndai P, Goel A, Liu H, Roy K. An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 841-846. DOI: 10.1109/ASPDAC.2009.4796585  0.623
2008 Ghosh S, Choi JH, Ndai P, Roy K. O2C: Occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors Proceedings of the International Symposium On Low Power Electronics and Design. 189-192. DOI: 10.1145/1393921.1393971  0.408
2008 Ndai P, Bhunia S, Agarwal A, Roy K. Within-die variation-aware scheduling in superscalar processors for improved throughput Ieee Transactions On Computers. 57: 940-951. DOI: 10.1109/Tc.2008.40  0.602
2008 Ghosh S, Ndai P, Roy K. A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking Proceedings -Design, Automation and Test in Europe, Date. 366-371. DOI: 10.1109/DATE.2008.4484707  0.352
2007 Ndai P, Lu SL, Somesekhar D, Roy K. Fine-grained redundancy in adders Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 317-321. DOI: 10.1109/ISQED.2007.75  0.386
2007 Ghosh S, NDai P, Bhunia S, Roy K. Tolerance to small delay defects by adaptive clock stretching Proceedings - Iolts 2007 13th Ieee International On-Line Testing Symposium. 244-249. DOI: 10.1109/IOLTS.2007.67  0.649
2005 Ndai P, Agarwal A, Chen Q, Roy K. A soft error monitor using switching current detection Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 185-190. DOI: 10.1109/ICCD.2005.15  0.38
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