Li-Shiuan Peh, Ph.D. - US grants

Power is becoming increasingly as important, if not more important than
performance in many digital systems ranging from PCs and servers to
Internet routers and embedded systems-on-a-chip. While there has been
substantial research exploring the power efficiency of the processing
and memory elements of digital systems, research investigating the power
consumption of communication elements has been lagging. As a wide range
of digital systems becomes increasingly interconnected, it is now
both timely and critical to explore power-aware interconnection networks.

In this proposal, we outline our plans to research, develop and build
self-regulating power-aware interconnection networks that trade off
power and performance automatically while meeting design constraints. In
these networks, power-aware router and link mechanisms export knobs by
which network power and performance can be adjusted. Policies then
control these knobs to deliver network power-performance that meet
design goals. Self-regulating power-aware networks alleviate designers
from the daunting task of reconciling two highly divergent goals -
high performance, and low power.

In highlighting and demonstrating the importance of power awareness in
networks, our proposed research advances a deeper understanding of
networks from a fresh perspective, with a potential for high-impact
contributions in research. In addition, we see our research leading to
power efficiency being an integral part of networking curriculum.

Abstract:
Interconnection network fabrics are becoming an ever-more critical
communication backbone of many digital systems, providing the means for
systems to scale up in capacity. As these systems become
power-constrained, networks stand to be the weakest link, unless there
is a shift from prior performance-driven approaches to one that focuses
on the power efficiency of networks.

This project takes a multi-level approach to power-efficient interconnection
networks that synergistically bridges research in circuits, architecture
and software, providing a complete solution that will make power-aware
network fabrics a reality. Research into novel low-power circuit
techniques develops basic network building blocks for new
power-efficient network architecture designs. New link and switch
mechanisms uncovered at the circuit-level are leveraged for
run-time architectural tradeoffs in network power and performance.
Higher up in the hierarchy, the software level closest to users
analyzes and factors in user power-performance requirements.

This research targets a diverse range of systems -- (1) both
general-purpose and embedded systems; (2) both electrical and optical
networking technologies, seeking to determine the optimal choice between
optical versus electrical interconnection at each level in the network
hierarchy from a power perspective; (3) from tiny on-chip networks to
data center-wide chassis-to-chassis networks.

The research is integrated into the education curriculum,
through existing and new graduate courses, and in undergraduate research
programs. The project seeks to further broaden the participation of
underrepresented groups in research activities. As a pioneering effort in
power-efficient interconnection networks, the project seeks to
facilitate future research and education in this area through the
release of simulation tools and other results.

Today's embedded systems have been designed in an ad hoc manner, each system re-designed from scratch to handle new system and software requirements. As requirements for embedded systems are changing rapidly, a key challenge is to develop general design methodologies that can scale to new VLSI technologies such as multiple cores on a billion-transistor embedded chip, new power-performance targets, and new-generation software systems.

This research proposes a flow-based embedded system that focuses on an execution model based on flows and a corresponding embedded system platform based on the flow execution model. In a flow-based embedded system, the hardware dynamically adapts to (1) heterogeneity in an embedded system and (2) energy constraints while ensuring (3) real-time deadlines are met, and (4) the software is shielded from all the above hardware complexities through the flow execution model, and is thus (5) portable across hardware generations. Flows indicate all potential partition points in an application; thus they expose points that allow the systems software (and supporting hardware) to dynamically adapt the actual partitioning or parallelism in the face of real-time deadlines, energy and reliability constraints, and heterogeneity. The scope of the project includes investigating flow-parallelizing compiling techniques that automatically extract flows from sequential code, novel hardware mechanisms that ensure low-overhead dynamic execution adaptation, lightweight OS support for the flow model across a range of embedded applications.

Increasingly, computing trends are leading to a new class of distributed
and highly-dynamic applications in which spatial-awareness plays a central role.
Spatially-aware applications rely on absolute or relative information about the geographic position of compute devices in order to support novel functionality. While many spatial application drivers already exist in mobile and distributed computing, very little support exists for programming these applications, expressing their spatial and temporal constraints, and supporting optimization layers for efficient implementation on real-world, highly-dynamic platforms.
This research addresses these shortcomings by providing language- and
system-layer support for expressing and optimizing spatial applications.
Since spatial computing is inherently distributed, close attention is given to resource sharing and management within and across programs.

The project's SARANA system architecture includes (i) a programming language that allows users to express the spatial region of interest and the quality of
result required, (ii) a compiler that can optimize the program so it uses resources more efficiently, and (iii) a runtime system that dynamically installs and migrates the program onto physical nodes whose resource availability match its resource needs.
A resource cost model permeates all the system layers of SARANA, permitting users to express their resource needs and quality of result requirements in terms of cost-benefit tradeoffs. . The runtime system prices resources and services, in order to broker agreements regarding resource needs and availability.
SARANA's driving applications include an early warning system to find
abducted children (Amber Alert), an earthquake monitoring system, and
multi-user gaming networks.

This award is aimed to aid US students to attend the ACM/IEEE 35th Annual International Symposium
on Computer Architecture which will be held in Beijing, China, in June 2008.
The ACM/IEEE Annual International Symposium on Computer Architecture (ISCA) is the flagship conference in
computer architecture and its conference proceedings are viewed as the most prestigious publication venue in the
computer architecture community. The symposia started in 1973 and it has been sponsored by the two most
important academic organizations in computer architecture, the Special Interest Group on Computer Architecture
(SIGARCH) of the Association for Computing Machinery (ACM) and the Technical Committee on Computer
Architecture (TCCA) of the Institute of Electrical and Electronics Engineers (IEEE). The majority of historically
high-impact publications on computer architecture have been published in this conference.
It is a significant event that the 35th Annual Symposium of ISCA will be held in Beijing, China, in June 2008.
This will be the first ISCA meeting held in China since the symposia started in 1973.
This award will assist deserving students to attend and present their work at the meeting.