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Donald Yeung

Affiliations:

Electrical and Computer Engineering

University of Maryland, College Park, College Park, MD

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Parents

Children

Dongkeun Kim	grad student	2004	University of Maryland
Seungryul Choi	grad student	2006	University of Maryland
Xuanhua Li	grad student	2009	University of Maryland
Wanli Liu	grad student	2009	University of Maryland
Meng-Ju Wu	grad student	2012	University of Maryland
Abdel-Hameed A. Badawy	grad student	2013	University of Maryland
Inseok S. Choi	grad student	2014	University of Maryland

Collaborators

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Publications

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Gerzhoy D, Sun X, Zuzak M, et al. (2020) Nested MIMD-SIMD Parallelization for Heterogeneous Microprocessors Acm Transactions On Architecture and Code Optimization. 16: 1-27
Jagasivamani M, Walden C, Singh D, et al. (2019) Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die Ieee Micro. 39: 64-72
Zhao M, Yeung D. (2017) Using Multicore Reuse Distance to Study Coherence Directories Acm Transactions On Computer Systems. 35: 4
Badawy AA, Yeung D. (2017) Guiding Locality Optimizations for Graph Computations via Reuse Distance Analysis Ieee Computer Architecture Letters. 16: 119-122
Choi IS, Yeung D. (2017) Multi-cache resizing via greedy coordinate descent The Journal of Supercomputing. 73: 2402-2429
Badamo M, Casarona J, Zhao M, et al. (2016) Identifying Power-Efficient Multicore Cache Hierarchies via Reuse Distance Analysis Acm Transactions On Computer Systems. 34: 3
Zhen Y, Gao Y, Yeung DY, et al. (2015) Spectral Multimodal Hashing and Its Application to Multimedia Retrieval. Ieee Transactions On Cybernetics
Wu MJ, Yeung D. (2013) Efficient reuse distance analysis of multicore scaling for loop-based parallel programs Acm Transactions On Computer Systems. 31
Li X, Yeung DF, Fiegen AM, et al. (2011) Determinants of the higher order association of the restriction factor TRIM5alpha and other tripartite motif (TRIM) proteins. The Journal of Biological Chemistry. 286: 27959-70
Choi I, Zhao M, Yang X, et al. (2011) Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor Ieee Computer Architecture Letters. 10: 45-48

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