Changhoon Choi, Ph.D.
Affiliations: | 2002 | Stanford University, Palo Alto, CA |
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"Changhoon Choi"Parents
Sign in to add mentor| Robert W. Dutton | grad student | 2002 | Stanford | |
| (Modeling of nanoscale MOSFETs.) | ||||
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Publications
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| Choi C, Chun J, Dutton RW. (2004) Electrothermal characteristics of strained-Si MOSFETs in high-current operation Ieee Transactions On Electron Devices. 51: 1928-1931 |
| Choi C, Yu Z, Dutton RW. (2003) Resonant gate tunneling current in double-gate SOI: a simulation study Ieee Transactions On Electron Devices. 50: 2579-2581 |
| Choi C, Yu Z, Dutton RW. (2003) Impact of poly-gate depletion on MOS RF linearity Ieee Electron Device Letters. 24: 330-332 |
| Choi CH, Chidambaram PR, Khamankar R, et al. (2002) Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS Ieee Transactions On Electron Devices. 49: 1227-1231 |
| Kwong MY, Choi C, Kasnavi R, et al. (2002) Series resistance calculation for source/drain extension regions using 2-D device simulation Ieee Transactions On Electron Devices. 49: 1219-1226 |
| Choi CH, Chidambaram PR, Khamankar R, et al. (2002) Gate length dependent polysilicon depletion effects Ieee Electron Device Letters. 23: 224-226 |
| Goo J, Choi C, Abramo A, et al. (2001) Physical origin of the excess thermal noise in short channel MOSFETs Ieee Electron Device Letters. 22: 101-103 |
| Choi C, Nam K, Yu Z, et al. (2001) Impact of gate direct tunneling current on circuit performance: a simulation study Ieee Transactions On Electron Devices. 48: 2823-2829 |
| Goo J, Choi C, Danneville F, et al. (2000) An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs Ieee Transactions On Electron Devices. 47: 2410-2419 |
| Choi CH, Wu Y, Goo JS, et al. (2000) Capacitance reconstruction from measured C-V in high leakage, nitride/oxide MOS Ieee Transactions On Electron Devices. 47: 1843-1850 |