Srikanth Gondi, Ph.D.
Affiliations: | 2006 | University of California, Los Angeles, Los Angeles, CA |
Area:
Analog, RF, mixed-signal integrated circuit design, dual-standard RF transceivers, phase-locked systems and frequency synthesizers, A/D and D/A converters, high-speed data communication circuitsGoogle:
"Srikanth Gondi"Parents
Sign in to add mentor| Behzad Razavi | grad student | 2006 | UCLA | |
| (Equalization and clock and data recovery techniques for serial -link receivers.) | ||||
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Publications
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| Nishi Y, Abe K, Ribo J, et al. (2008) An ASIC-Ready 1.25-6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility Proceedings of 2008 Ieee Asian Solid-State Circuits Conference, a-Sscc 2008. 37-40 |
| Gondi S, Razavi B. (2007) Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers Ieee Journal of Solid-State Circuits. 42: 1999-2010 |
| Gondi S, Razavi B. (2006) A 10-Gb/s CMOS merged adaptive equalizer/CDR circuit for serial-link receivers Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 194-195 |
| Gondi S, Lee J, Takeuchi D, et al. (2005) A 10Gb/s CMOS adaptive equalizer for backplane applications Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 48: 328-329+601 |
| Gondi S, Lee J, Takeuchi D, et al. (2005) A 10Gb/s CMOS adaptive equalizer for backplane applications Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 48: 328-329+601 |
| Gondi S, Geiger R, Liu J, et al. (2002) A 2V low-power CMOS 125Mbaud repeater architecture for UTP5 cables European Solid-State Circuits Conference. 571-574 |