Ahmed Shebaita, Ph.D.
Affiliations: | 2008 | Electrical and Computer Engineering | Northwestern University, Evanston, IL |
| 2008- | IBM Corporation |
Area:
Electronics and Electrical EngineeringGoogle:
"Ahmed Shebaita"Parents
Sign in to add mentor| Yehea I. Ismail | grad student | 2008 | Northwestern | |
| (Timing analysis and optimization techniques for high performance integrated circuits.) | ||||
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Publications
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| Das D, Shebaita A, Zhou H, et al. (2011) FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 443-456 |
| Shebaita A, Das D, Petranovic D, et al. (2011) A novel moment based framework for accurate and efficient static timing analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1258-1262 |
| Shebaita A, Ismail Y. (2009) Lower power, lower delay design scheme for cmos tapered buffers 2009 4th International Design and Test Workshop, Idt 2009 |
| Shebaita A, Petranovic D, Ismail Y. (2009) An s-domain based framework for accurate and efficient static waveform analysis 2009 4th International Design and Test Workshop, Idt 2009 |
| Shebaita A, Ismail Y. (2008) Multiple threshold voltage design scheme for CMOS tapered buffers Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 21-25 |
| Shebaita A, Petranovic D, Ismail Y. (2008) A novel moment-based methodology for accurate and efficient static timing analysis Proceedings - 2008 Ieee International Conference On Integrated Circuit Design and Technology, Icicdt. 293-296 |
| Das D, Shebaita A, Ismail Y, et al. (2007) NostraXtalk: A predictive framework for accurate static timing analysis in udsm vlsi circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 25-30 |
| Shebaita A, Petranovic D, Ismail Y. (2007) Including inductance in static timing analysis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 686-691 |
| Shebaita A, Ismail Y. (2007) Variable threshold voltage design scheme for CMOS tapered buffers Proceedings - Ieee International Symposium On Circuits and Systems. 1385-1388 |
| Das D, Shebaita A, Zhou H, et al. (2006) FA-STAC: A framework for fast and accurate static timing analysis with coupling Ieee International Conference On Computer Design, Iccd 2006. 43-49 |