Suboh Suboh, Ph.D.
Affiliations: | 2010 | Computer Engineering | The George Washington University, Washington, DC, United States |
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"Suboh Suboh"Parents
Sign in to add mentor| Tarek El-Ghazawi | grad student | 2010 | The George Washington University | |
| (Towards an adaptive interconnect for system-on-chip.) | ||||
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Publications
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| Suboh S, Narayana V, Bakhouya M, et al. (2014) Methodology for adapting on-chip interconnect architectures Iet Circuits, Devices and Systems. 8: 109-117 |
| Aldahlawi A, El-Araby E, Suboh S, et al. (2012) An Empirical and Architectural Study of Using an SSD-Aware Hybrid Storage System to Improve the Performance of the Data Intensive Applications International Journal of Information Engineering and Electronic Business |
| Suboh SA, Narayana VK, Bakhouya M, et al. (2012) A scalability study of interconnect architectures for system-on-chip Proceedings of the 2012 International Conference On High Performance Computing and Simulation, Hpcs 2012. 300-306 |
| Aldahlawi A, El-Araby E, Suboh S, et al. (2011) Modelling the performance of an SSD-aware storage system using least squares regression Proceedings of Ieee/Acs International Conference On Computer Systems and Applications, Aiccsa. 181-187 |
| Bakhouya M, Suboh S, Gaber J, et al. (2011) Performance evaluation and design tradeoffs of on-chip interconnect architectures Simulation Modelling Practice and Theory. 19: 1496-1505 |
| Bakhouya M, Suboh S, Gaber J, et al. (2010) Analytical performance comparison of 2D mesh, WK-recursive, and spidergon NoCs Proceedings of the 2010 Ieee International Symposium On Parallel and Distributed Processing, Workshops and Phd Forum, Ipdpsw 2010 |
| Suboh S, Bakhouya M, Gaber J, et al. (2010) Analytical modeling and evaluation of network-on-chip architectures Proceedings of the 2010 International Conference On High Performance Computing and Simulation, Hpcs 2010. 615-622 |
| Bakhouya M, Suboh S, Gaber J, et al. (2009) Analytical modeling and evaluation of on-chip interconnects using network calculus Proceedings - 2009 3rd Acm/Ieee International Symposium On Networks-On-Chip, Nocs 2009. 74-79 |
| Suboh S, Bakhouya M, Lopez-Buedo S, et al. (2008) Simulation-based approach for evaluating on-chip interconnect architectures Proceedings - 2008 4th Southern Conference On Programmable Logic, Spl. 75-80 |
| Suboh S, Bakhouya M, El-Ghazawi T. (2008) Simulation and evaluation of on-chip interconnect architectures: 2D mesh, Spidergon, and WK-recursive network Proceedings - Second Ieee International Symposium On Networks-On-Chip, Nocs 2008. 205-206 |