Brandon Noia, Ph.D.
Affiliations: | 2014 | Electrical and Computer Engineering | Duke University, Durham, NC |
Area:
Electronics and Electrical Engineering, Computer EngineeringGoogle:
"Brandon Noia"Parents
Sign in to add mentor| Krishnendu Chakrabarty | grad student | 2014 | Duke | |
| (Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.) | ||||
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Publications
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| Noia B, Panth S, Chakrabarty K, et al. (2015) Scan test of die logic in 3-D ICs using TSV probing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 317-330 |
| Chakrabarty K, Agrawal M, Deutsch S, et al. (2014) Test and Design-for-Testability Solutions for 3D Integrated Circuits Ipsj Transactions On System Lsi Design Methodology. 7: 56-73 |
| Noia B, Chakrabarty K. (2014) Retiming for delay recovery after DfT insertion on interdie paths in 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 464-475 |
| Noia B, Chakrabarty K. (2013) Pre-bond probing of through-silicon vias in 3-D stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 547-558 |
| Noia B, Chakrabarty K, Goel SK, et al. (2011) Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1705-1718 |
| Noia B, Chakrabarty K. (2011) Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips Iet Computers & Digital Techniques. 5: 186 |
| Noia B, Chakrabarty K, Marinissen EJ. (2011) Optimization Methods for Post-Bond Testing of 3D Stacked ICs Journal of Electronic Testing. 28: 103-120 |