Avesta Sasan, Ph.D.
Affiliations: | 2010 | Electrical and Computer Engineering - Ph.D. | University of California, Irvine, Irvine, CA |
Area:
Electronics and Electrical Engineering, Computer EngineeringGoogle:
"Avesta Sasan"Parents
Sign in to add mentor| Fadi J. Kurdahi | grad student | 2010 | UC Irvine | |
| (Low power and process variation aware SRAM and Cache design fault tolerance in SRAM circuit, architecture and organization.) | ||||
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Publications
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| Malik M, Sasan A, Joshi R, et al. (2016) Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations Ispass 2016 - International Symposium On Performance Analysis of Systems and Software. 153-154 |
| Malik M, Rafatirah S, Sasan A, et al. (2015) System and architecture level characterization of big data applications on big and little core server architectures Proceedings - 2015 Ieee International Conference On Big Data, Ieee Big Data 2015. 85-94 |
| Sasan A, Kurhadi FJ, Eltawil AM. (2015) Resizable data composer (RDC) cache: A near-threshold cache tolerating process variation via architectural fault tolerance Near Threshold Computing: Technology, Methods and Applications. 57-73 |
| Sasan A, Amiri K, Homayoun H, et al. (2012) Variation trained drowsy cache (VTD-cache): A history trained variation aware drowsy cache for fine grain voltage scaling Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 630-642 |
| Sasan A, Homayoun H, Amiri K, et al. (2012) History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring Proceedings - International Symposium On Quality Electronic Design, Isqed. 498-505 |
| Homayoun H, Sasan A, Veidenbaum AV, et al. (2011) MZZ-HVS: Multiple sleep modes zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 2303-2316 |
| Homayoun H, Sasan A, Gaudiot JL, et al. (2011) Reducing power in all major CAM and SRAM-based processor units via centralized, dynamic resource size management Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 2081-2094 |
| Sasan A, Homayoun H, Eltawil AM, et al. (2011) Inquisitive defect cache: A means of combating manufacturing induced process variation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1597-1609 |
| Homayoun H, Sasan A, Gupta A, et al. (2010) Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units Cf 2010 - Proceedings of the 2010 Computing Frontiers Conference. 297-307 |
| Homayoun H, Gupta A, Veidenbaum A, et al. (2010) RELOCATE: Register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5952: 216-231 |