ParentsSign in to add mentor
ChildrenSign in to add trainee
CollaboratorsSign in to add collaborator
BETA: Related publications
You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect.
|Vasudevan S, Viswanath V, Sumners RW, et al. (2007) Automatic verification of arithmetic circuits in RTL using stepwise refinement of term rewriting systems Ieee Transactions On Computers. 56: 1401-1414|