Victor Adler
Affiliations: | 1998 | Electrical and Computer Engineering | University of Rochester, Rochester, NY |
1998- | Sun Microsystems |
Area:
Thesis: Repeater Insertion for Driving Resistive Interconnect in CMOS VLSI CircuitsGoogle:
"Victor Adler"Parents
Sign in to add mentorEby G. Friedman | grad student | 1998 | Rochester | |
(Thesis: Repeater Insertion for Driving Resistive Interconnect in CMOS VLSI Circuits) |
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Publications
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Velenis D, Tang KT, Kourtev IS, et al. (2002) Demonstration of speed and power enhancements on an industrial circuit through application of clock skew scheduling Journal of Circuits, Systems and Computers. 11: 231-245 |
Velenis D, Tang KT, Kourtev IS, et al. (2001) Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths Proceedings of the Annual Ieee International Asic Conference and Exhibit. 30-33 |
Velenis D, Tang KT, Kourtev IS, et al. (2001) Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2: 1021-1025 |
Adler V, Friedman EG. (2000) Uniform repeater insertion in RC trees Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 47: 1515-1523 |
Gaj K, Herr QP, Adler V, et al. (1999) Toward a systematic design methodology for large multigigahertz rapid single flux quantum circuits Ieee Transactions On Applied Superconductivity. 9: 4591-4606 |
Gaj K, Herr QP, Adler V, et al. (1999) Tools for the computer-aided design of multigigahertz superconducting digital circuits Ieee Transactions On Applied Superconductivity. 9: 18-38 |
Adler V, Friedman EG. (1998) Repeater design to reduce delay and power in resistive interconnect Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 45: 607-616 |
Adler V, Friedman EG. (1997) Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load Analog Integrated Circuits and Signal Processing. 14: 29-39 |