Rouying Zhan, Ph.D.
Affiliations: | 2005 | Illinois Institute of Technology, Chicago, IL, United States |
Area:
Electronics and Electrical EngineeringGoogle:
"Rouying Zhan"Parents
Sign in to add mentor| Albert Z. H. Wang | grad student | 2005 | Illinois Institute of Technology | |
| (ESDCat: A new CAD software package for full-chip ESD protection circuit design verification.) | ||||
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Publications
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| Li X, Xie H, Zhan R, et al. (2018) Effect of Double Bond Position on 2-Phenyl-benzofuran Antioxidants: A Comparative Study of Moracin C and Iso-Moracin C. Molecules (Basel, Switzerland). 23 |
| Wang AZH, Feng H, Zhan R, et al. (2005) A review on RF ESD protection design Ieee Transactions On Electron Devices. 52: 1304-1311 |
| Xie H, Feng H, Zhan R, et al. (2005) A new low-parasitic polysilicon SCR ESD protection structure for RF ICs Ieee Electron Device Letters. 26: 121-123 |
| Zhan R, Feng H, Wu Q, et al. (2004) ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1421-1428 |
| Chen G, Feng H, Xie H, et al. (2004) Characterizing diodes for RF ESD protection Ieee Electron Device Letters. 25: 323-325 |
| Zhan R, Feng H, Wu Q, et al. (2003) ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1362-1370 |
| Feng H, Chen G, Zhan R, et al. (2003) A mixed-mode ESD protection circuit simulation-design methodology Ieee Journal of Solid-State Circuits. 38: 995-1006 |
| Gong K, Feng H, Zhan R, et al. (2002) A study of parasitic effects of ESD protection on RF ICs Ieee Transactions On Microwave Theory and Techniques. 50: 393-402 |
| Feng H, Zhan R, Wu Q, et al. (2002) RC-SCR: Very-low-voltage ESD protection circuit in plain CMOS Electronics Letters. 38: 1099-1100 |
| Feng H, Zhan R, Gong K, et al. (2001) A new pad-oriented multiple-mode ESD protection structure and layout optimization Ieee Electron Device Letters. 22: 493-495 |