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Jerry G. Fossum

Affiliations: 
1978- Electrical and Computer Engineering University of Florida, Gainesville, Gainesville, FL, United States 
Area:
Electronics and Electrical Engineering, Computer Engineering
Website:
https://www.eng.ufl.edu/about/contact/college-directory/name/jerry-fossum/
Google:
""Jerry George Fossum""
Bio:

https://ieeexplore.ieee.org/author/37272082000
http://hdl.handle.net/10150/287799
https://www.proquest.com/openview/8e2b1be8d8bc07fa47cd71c014cf932e/1

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Parents

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Douglas James Hamilton grad student 1971 University of Arizona
 (Systematic Computer-aided Three-dimensional Modeling of Integrated Bipolar Devices)

Children

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Mario M. Pelella grad student 2000 UF Gainesville
Meng-Hsueh Chiang grad student 2001 UF Gainesville
Keunwoo Kim grad student 2001 UF Gainesville
Lixin Ge grad student 2002 UF Gainesville
Ji-Woon Yang grad student 2004 UF Gainesville
Vishal P. Trivedi grad student 2005 UF Gainesville
Murshed M. Chowdhury grad student 2006 UF Gainesville
Seung-Hwan Kim grad student 2006 UF Gainesville
Shishir Agrawal grad student 2009 UF Gainesville
Siddharth Chouksey grad student 2009 UF Gainesville
Zhichao Lu grad student 2010 UF Gainesville
Zhenming Zhou grad student 2010 UF Gainesville
Dabraj Sarkar grad student 2012 UF Gainesville

Collaborators

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Publications

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Huang Y, Chiang M, Wang S, et al. (2017) GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node Ieee Journal of the Electron Devices Society. 5: 164-169
Saha S, Onyegam EU, Sarkar D, et al. (2013) Exfoliated ∼25μm Si foil for solar cells with improved light-trapping Materials Research Society Symposium Proceedings. 1493: 51-58
Wu Q, Chen J, Lu Z, et al. (2012) Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories Ieee Electron Device Letters. 33: 743-745
Lu Z, Fossum JG, Zhou Z. (2011) A Floating-Body/Gate DRAM Cell Upgraded for Long Retention Time Ieee Electron Device Letters. 32: 731-733
Chouksey S, Fossum JG, Agrawal S. (2010) Insights on Design and Scalability of Thin-BOX FD/SOI CMOS Ieee Transactions On Electron Devices. 57: 2073-2079
Agrawal S, Fossum JG. (2010) A Physical Model for Fringe Capacitance in Double-Gate MOSFETs With Non-Abrupt Source/Drain Junctions and Gate Underlap Ieee Transactions On Electron Devices. 57: 1069-1075
Fossum JG, Zhou Z, Mathew L, et al. (2010) SOI versus bulk-silicon nanoscale FinFETs Solid-State Electronics. 54: 86-89
Chouksey S, Fossum JG, Behnam A, et al. (2009) Threshold Voltage Adjustment in Nanoscale DG FinFETs Via Limited Source/Drain Dopants in the Channel Ieee Transactions On Electron Devices. 56: 2348-2353
Zhou Z, Fossum JG, Lu Z. (2009) Physical Insights on BJT-Based 1T DRAM Cells Ieee Electron Device Letters. 30: 565-567
Lu Z, Fossum JG, Yang J, et al. (2009) A Simplified Superior Floating-Body/Gate DRAM Cell Ieee Electron Device Letters. 30: 282-284
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